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19185: cpu/gd32v: add periph_gpio_irq support r=gschorcht a=gschorcht ### Contribution description This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. ### Testing procedure Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash (until PR #19170 is merged only `seeedstudio ``` With the GPIO PB8 and PB9 connected, the following test sequence should work: ``` > init_out 1 8 > init_int 1 9 2 0 GPIO_PIN(1, 9) successfully initialized as ext int > set 1 8 INT: external interrupt from pin 9 > clear 1 8 INT: external interrupt from pin 9 ``` ### Issues/PRs references 19187: cpu/gd32v: add pm_layered support in periph_pm r=gschorcht a=gschorcht ### Contribution description This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103. Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs. ### Testing procedure The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing. ``` BOARD=seeedstudio-gd32 make -C tests/periph_pm flash ``` The test output should be: ``` main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 ``` Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds ``` > set_rtc 1 5 Setting power mode 1 for 5 seconds. ␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> ``` while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart. ``` > set_rtc 0 5 Setting power mode 0 for 5 seconds. main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test) ... mode 0 blockers: 1 mode 1 blockers: 2 mode 2 blockers: 0 Lowest allowed mode: 2 > ``` The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards. ### Issues/PRs references Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
65 lines
1.4 KiB
Plaintext
65 lines
1.4 KiB
Plaintext
# Copyright (c) 2020 Inria
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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#
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config CPU_FAM_GD32V
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bool
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select CPU_CORE_RV32IMAC
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select HAS_ARCH_NUCLEI
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select HAS_CPU_GD32V
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select HAS_PERIPH_CLIC
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select HAS_PERIPH_GPIO
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select HAS_PERIPH_GPIO_IRQ
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select HAS_PERIPH_FLASHPAGE
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select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
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select HAS_PERIPH_FLASHPAGE_PAGEWISE
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select HAS_PERIPH_PM
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select HAS_PERIPH_RTC
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select HAS_PERIPH_TIMER
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select HAS_PERIPH_TIMER_PERIODIC
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select HAS_PERIPH_WDT
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select MODULE_PERIPH_CLIC if TEST_KCONFIG
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select MODULE_PERIPH_WDT if MODULE_PERIPH_PM && HAS_PERIPH_WDT
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select PACKAGE_NMSIS_SDK
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menu "GD32V configuration"
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config CPU_MODEL_GD32VF103CBT6
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bool
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select CPU_FAM_GD32V
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config CPU_MODEL_GD32VF103VBT6
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bool
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select CPU_FAM_GD32V
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## Definition of specific features
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config HAS_CPU_GD32V
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bool
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help
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Indicates that a 'gd32v' cpu is being used.
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config CPU_FAM
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default "gd32v" if CPU_FAM_GD32V
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config CPU_MODEL
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default "gd32vf103cbt6" if CPU_MODEL_GD32VF103CBT6
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config CPU_MODEL
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default "gd32vf103vbt6" if CPU_MODEL_GD32VF103VBT6
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config CPU
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default "gd32v" if CPU_FAM_GD32V
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config CPU_CORE
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default "rv32imac" if CPU_CORE_RV32IMAC
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rsource "periph/Kconfig"
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endmenu
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source "$(RIOTCPU)/riscv_common/Kconfig"
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