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de486ff79f
Tested on the following Freescale Kinetis K60 CPUs: - MK60DN512VLL10 The port should with a high probability also support the following variations of the above CPUs (untested): - MK60DN256VLL10 And possibly also: - MK60DX256VLL10 - MK60DX512VLL10 - MK60DN512VLQ10 - MK60DN256VLQ10 - MK60DX256VLQ10 - MK60DN512VMC10 - MK60DN256VMC10 - MK60DX256VMC10 - MK60DN512VMD10 - MK60DX256VMD10 - MK60DN256VMD10 Currently not working on the following CPUs (Missing PIT channel chaining necessary for kinetis_common/periph/timer implementation): - MK60DN256ZVLL10 - MK60DN512ZVLL10 - MK60DX256ZVLL10 - MK60DX512ZVLL10 - MK60DN512ZVLQ10 - MK60DN256ZVLQ10 - MK60DX256ZVLQ10 - MK60DN512ZVMC10 - MK60DN256ZVMC10 - MK60DX256ZVMC10 - MK60DN512ZVMD10 - MK60DX256ZVMD10 - MK60DN256ZVMD10 Regarding header files from Freescale: dist/tools/licenses: Add Freescale CMSIS PAL license pattern Redistribution is OK according to: https://community.freescale.com/message/477976?et=watches.email.thread#477976 Archive copy in case the above link disappears: https://web.archive.org/web/20150328073057/https://community.freescale.com/message/477976?et=watches.email.thread Applies to: - MK60DZ10.h (K60 variant)
14 lines
490 B
Plaintext
14 lines
490 B
Plaintext
OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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MEMORY
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{
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vectors (rx) : ORIGIN = 0x0, LENGTH = 0x400
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flashsec (rx) : ORIGIN = 0x400, LENGTH = 0x10
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flash (rx) : ORIGIN = 0x410, LENGTH = 512K - 0x410
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sram_l (rwx) : ORIGIN = 0x20000000 - 64K, LENGTH = 64K /* Only accessible via code bus. */
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sram_u (rwx) : ORIGIN = 0x20000000, LENGTH = 64K /* Only accessible via system bus. */
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}
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INCLUDE kinetis-base.ld
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