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https://github.com/RIOT-OS/RIOT.git
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df37e69b90
Currently the cc2538 is based on from-scratch adaption which is
not feature complete and thus lacks defines etc. Introducing the
official vendor header will ease future extension and adaptions
of the CPU and its features.
265 lines
14 KiB
C
Executable File
265 lines
14 KiB
C
Executable File
/******************************************************************************
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* Filename: hw_smwdthrosc.h
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* Revised: $Date: 2013-04-30 17:13:44 +0200 (Tue, 30 Apr 2013) $
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* Revision: $Revision: 9943 $
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_SMWDTHROSC_H__
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#define __HW_SMWDTHROSC_H__
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//*****************************************************************************
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//
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// The following are defines for the SMWDTHROSC register offsets.
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//
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//*****************************************************************************
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#define SMWDTHROSC_WDCTL 0x400D5000 // Watchdog Timer Control
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#define SMWDTHROSC_ST0 0x400D5040 // Sleep Timer 0 count and compare
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#define SMWDTHROSC_ST1 0x400D5044 // Sleep Timer 1 count and compare
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#define SMWDTHROSC_ST2 0x400D5048 // Sleep Timer 2 count and compare
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#define SMWDTHROSC_ST3 0x400D504C // Sleep Timer 3 count and compare
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#define SMWDTHROSC_STLOAD 0x400D5050 // Sleep Timer load status
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#define SMWDTHROSC_STCC 0x400D5054 // Sleep Timer Capture control
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#define SMWDTHROSC_STCS 0x400D5058 // Sleep Timer Capture status
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#define SMWDTHROSC_STCV0 0x400D505C // Sleep Timer Capture value byte
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// 0
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#define SMWDTHROSC_STCV1 0x400D5060 // Sleep Timer Capture value byte
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// 1
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#define SMWDTHROSC_STCV2 0x400D5064 // Sleep Timer Capture value byte
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// 2
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#define SMWDTHROSC_STCV3 0x400D5068 // Sleep Timer Capture value byte
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// 3
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SMWDTHROSC_WDCTL register.
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//
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//*****************************************************************************
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#define SMWDTHROSC_WDCTL_CLR_M 0x000000F0 // Clear timer When 0xA followed
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// by 0x5 is written to these bits,
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// the timer is loaded with 0x0000.
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// Note that 0x5 must be written
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// within one watchdog clock period
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// Twdt after 0xA was written for
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// the clearing to take effect
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// (ensured). If 0x5 is written
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// between Twdt and 2Twdt after 0xA
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// was written, the clearing may
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// take effect, but there is no
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// guarantee. If 0x5 is written >
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// 2Twdt after 0xA was written, the
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// timer will not be cleared. If a
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// value other than 0x5 is written
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// after 0xA has been written, the
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// clear sequence is aborted. If
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// 0xA is written, this starts a
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// new clear sequence. Writing to
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// these bits when EN = 0 has no
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// effect.
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#define SMWDTHROSC_WDCTL_CLR_S 4
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#define SMWDTHROSC_WDCTL_EN 0x00000008 // Enable timer When 1 is written
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// to this bit the timer is enabled
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// and starts incrementing. The
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// interval setting specified by
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// INT[1:0] is used. Writing 0 to
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// this bit have no effect.
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#define SMWDTHROSC_WDCTL_EN_M 0x00000008
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#define SMWDTHROSC_WDCTL_EN_S 3
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#define SMWDTHROSC_WDCTL_INT_M 0x00000003 // Timer interval select These
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// bits select the timer interval
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// as follows: 00: Twdt x 32768 01:
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// Twdt x 8192 10: Twdt x 512 11:
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// Twdt x 64 Writing these bits
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// when EN = 1 has no effect.
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#define SMWDTHROSC_WDCTL_INT_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SMWDTHROSC_ST0 register.
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//
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//*****************************************************************************
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#define SMWDTHROSC_ST0_ST0_M 0x000000FF // Sleep Timer count and compare
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// value. When read, this register
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// returns the low bits [7:0] of
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// the Sleep Timer count. When
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// writing this register sets the
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// low bits [7:0] of the compare
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// value.
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#define SMWDTHROSC_ST0_ST0_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SMWDTHROSC_ST1 register.
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//
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//*****************************************************************************
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#define SMWDTHROSC_ST1_ST1_M 0x000000FF // Sleep Timer count and compare
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// value When read, this register
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// returns the middle bits [15:8]
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// of the Sleep Timer count. When
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// writing this register sets the
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// middle bits [15:8] of the
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// compare value. The value read is
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// latched at the time of reading
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// register ST0. The value written
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// is latched when ST0 is written.
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#define SMWDTHROSC_ST1_ST1_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SMWDTHROSC_ST2 register.
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//
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//*****************************************************************************
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#define SMWDTHROSC_ST2_ST2_M 0x000000FF // Sleep Timer count and compare
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// value When read, this register
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// returns the high bits [23:16] of
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// the Sleep Timer count. When
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// writing this register sets the
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// high bits [23:16] of the compare
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// value. The value read is latched
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// at the time of reading register
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// ST0. The value written is
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// latched when ST0 is written.
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#define SMWDTHROSC_ST2_ST2_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SMWDTHROSC_ST3 register.
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//
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//*****************************************************************************
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#define SMWDTHROSC_ST3_ST3_M 0x000000FF // Sleep Timer count and compare
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// value When read, this register
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// returns the high bits [31:24] of
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// the Sleep Timer count. When
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// writing this register sets the
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// high bits [31:24] of the compare
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// value. The value read is latched
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// at the time of reading register
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// ST0. The value written is
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// latched when ST0 is written.
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#define SMWDTHROSC_ST3_ST3_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SMWDTHROSC_STLOAD register.
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//
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//*****************************************************************************
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#define SMWDTHROSC_STLOAD_STLOAD \
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0x00000001 // Status signal for when STx
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// registers have been uploaded to
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// 32-kHz counter. 1: Load is
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// complete 0: Load is busy and STx
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// regs are blocked for writing
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#define SMWDTHROSC_STLOAD_STLOAD_M \
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0x00000001
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#define SMWDTHROSC_STLOAD_STLOAD_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SMWDTHROSC_STCC register.
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//
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//*****************************************************************************
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#define SMWDTHROSC_STCC_PORT_M 0x00000038 // Port select Valid settings are
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// 0-3, all others inhibit any
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// capture from occurring 000: Port
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// A selected 001: Port B selected
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// 010: Port C selected 011: Port D
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// selected
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#define SMWDTHROSC_STCC_PORT_S 3
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#define SMWDTHROSC_STCC_PIN_M 0x00000007 // Pin select Valid settings are
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// 1-7 when either port A, B, C, or
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// D is selected.
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#define SMWDTHROSC_STCC_PIN_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SMWDTHROSC_STCS register.
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//
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//*****************************************************************************
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#define SMWDTHROSC_STCS_VALID 0x00000001 // Capture valid flag Set to 1
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// when capture value in STCV has
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// been updated Clear explicitly to
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// allow new capture
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#define SMWDTHROSC_STCS_VALID_M 0x00000001
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#define SMWDTHROSC_STCS_VALID_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SMWDTHROSC_STCV0 register.
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//
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//*****************************************************************************
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#define SMWDTHROSC_STCV0_STCV0_M \
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0x000000FF // Bits [7:0] of Sleep Timer
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// capture value
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#define SMWDTHROSC_STCV0_STCV0_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SMWDTHROSC_STCV1 register.
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//
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//*****************************************************************************
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#define SMWDTHROSC_STCV1_STCV1_M \
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0x000000FF // Bits [15:8] of Sleep Timer
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// capture value
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#define SMWDTHROSC_STCV1_STCV1_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SMWDTHROSC_STCV2 register.
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//
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//*****************************************************************************
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#define SMWDTHROSC_STCV2_STCV2_M \
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0x000000FF // Bits [23:16] of Sleep Timer
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// capture value
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#define SMWDTHROSC_STCV2_STCV2_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the
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// SMWDTHROSC_STCV3 register.
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//
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//*****************************************************************************
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#define SMWDTHROSC_STCV3_STCV3_M \
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0x000000FF // Bits [32:24] of Sleep Timer
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// capture value
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#define SMWDTHROSC_STCV3_STCV3_S 0
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#endif // __HW_SMWDTHROSC_H__
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