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https://github.com/RIOT-OS/RIOT.git
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df37e69b90
Currently the cc2538 is based on from-scratch adaption which is
not feature complete and thus lacks defines etc. Introducing the
official vendor header will ease future extension and adaptions
of the CPU and its features.
86 lines
4.2 KiB
C
Executable File
86 lines
4.2 KiB
C
Executable File
/******************************************************************************
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* Filename: hw_memmap.h
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* Revised: $Date: 2013-04-12 15:10:54 +0200 (Fri, 12 Apr 2013) $
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* Revision: $Revision: 9735 $
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*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_MEMMAP_H__
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#define __HW_MEMMAP_H__
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//*****************************************************************************
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//
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// The following are defines for the base address of the memories and
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// peripherals on the top_s interface.
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//
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//*****************************************************************************
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#define ROM_BASE 0x00000000 // ROM
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#define FLASH_BASE 0x00200000 // Flash
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#define SRAM_BASE 0x20000000 // SRAM
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#define SRAM_LL_BASE 0x20004000 // SRAM_LL
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#define SSI0_BASE 0x40008000 // SSI
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#define SSI1_BASE 0x40009000 // SSI
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#define UART0_BASE 0x4000C000 // UART
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#define UART1_BASE 0x4000D000 // UART
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#define I2C_M0_BASE 0x40020000 // I2CM
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#define I2C_S0_BASE 0x40020800 // I2CS
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#define GPTIMER0_BASE 0x40030000 // GPTIMER
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#define GPTIMER1_BASE 0x40031000 // GPTIMER
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#define GPTIMER2_BASE 0x40032000 // GPTIMER
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#define GPTIMER3_BASE 0x40033000 // GPTIMER
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#define RFCORE_RAM_BASE 0x40088000 // SRAM_RFCORE
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#define FRMF_SRCM_RAM_BASE 0x40088400 // SRAM_FRMF_SRCM
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#define RFCORE_FFSM_BASE 0x40088500 // RFCORE_FFSM
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#define RFCORE_XREG_BASE 0x40088600 // RFCORE_XREG
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#define RFCORE_SFR_BASE 0x40088800 // RFCORE_SFR
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#define USB_BASE 0x40089000 // USB
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#define AES_BASE 0x4008B000 // AES
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#define SYS_CTRL_BASE 0x400D2000 // SYS_CTRL
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#define FLASH_CTRL_BASE 0x400D3000 // FLASH_CTRL
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#define IOC_BASE 0x400D4000 // IOC
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#define SMWDTHROSC_BASE 0x400D5000 // SMWDTHROSC
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#define ANA_REGS_BASE 0x400D6000 // ANA_REGS
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#define SOC_ADC_BASE 0x400D7000 // SOC_ADC
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#define GPIO_A_BASE 0x400D9000 // GPIO
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#define GPIO_B_BASE 0x400DA000 // GPIO
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#define GPIO_C_BASE 0x400DB000 // GPIO
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#define GPIO_D_BASE 0x400DC000 // GPIO
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#define uDMA_BASE 0x400FF000 // UDMA
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#define ST_TESTCTRL_BASE 0x40110000 // STTEST
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#define PKA_BASE 0x44004000 // PKA
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#define PKA_RAM_BASE 0x44006000 // SRAM_PKA
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#define CC_TESTCTRL_BASE 0x44010000 // CCTEST
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#endif // __HW_MEMMAP_H__
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