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dd88935f46
Previously sometimes `msp_` was used as prefix, sometimes `msp430_`. This makes the naming consistent.
126 lines
2.9 KiB
C
126 lines
2.9 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_msp430_f2xx_g2xx
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* @ingroup drivers_periph_uart
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* @{
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*
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* @file
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* @brief Low-level UART driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include "cpu.h"
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#include "periph_cpu.h"
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#include "periph_conf.h"
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#include "periph/uart.h"
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/**
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* @brief Keep track of the interrupt context
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* @{
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*/
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static uart_rx_cb_t ctx_rx_cb;
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static void *ctx_isr_arg;
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/** @} */
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static int init_base(uart_t uart, uint32_t baudrate);
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int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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{
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if (init_base(uart, baudrate) < 0) {
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return -1;
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}
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/* save interrupt context */
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ctx_rx_cb = rx_cb;
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ctx_isr_arg = arg;
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/* reset interrupt flags and enable RX interrupt */
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UART_IF &= ~(UART_IE_RX_BIT);
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UART_IF |= (UART_IE_TX_BIT);
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UART_IE |= (UART_IE_RX_BIT);
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UART_IE &= ~(UART_IE_TX_BIT);
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return 0;
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}
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static int init_base(uart_t uart, uint32_t baudrate)
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{
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if (uart != 0) {
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return -1;
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}
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/* get the default UART for now -> TODO: enable for multiple devices */
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msp430_usci_a_t *dev = UART_BASE;
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/* put device in reset mode while configuration is going on */
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dev->CTL1 = UCSWRST;
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/* configure to UART, using SMCLK in 8N1 mode */
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dev->CTL1 |= UCSSEL_SMCLK;
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dev->CTL0 = 0;
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dev->STAT = 0;
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/* configure baudrate */
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uint32_t base = ((msp430_submain_clock_freq() << 7) / baudrate);
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uint16_t br = (uint16_t)(base >> 7);
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uint8_t brs = (((base & 0x3f) * 8) >> 7);
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dev->BR0 = (uint8_t)br;
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dev->BR1 = (uint8_t)(br >> 8);
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dev->MCTL = (brs << UCBRS_POS);
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/* pin configuration -> TODO: move to GPIO driver once implemented */
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UART_RX_PORT->SEL |= UART_RX_PIN;
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UART_TX_PORT->SEL |= UART_TX_PIN;
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UART_RX_PORT->base.DIR &= ~(UART_RX_PIN);
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UART_TX_PORT->base.DIR |= UART_TX_PIN;
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/* releasing the software reset bit starts the UART */
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dev->CTL1 &= ~(UCSWRST);
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return 0;
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}
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void uart_write(uart_t uart, const uint8_t *data, size_t len)
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{
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(void)uart;
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for (size_t i = 0; i < len; i++) {
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while (!(UART_IF & UART_IE_TX_BIT)) {}
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UART_BASE->TXBUF = data[i];
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}
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}
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void uart_poweron(uart_t uart)
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{
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(void)uart;
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/* n/a */
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}
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void uart_poweroff(uart_t uart)
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{
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(void)uart;
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/* n/a */
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}
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ISR(UART_RX_ISR, isr_uart_0_rx)
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{
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__enter_isr();
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uint8_t stat = UART_BASE->STAT;
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uint8_t data = (uint8_t)UART_BASE->RXBUF;
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if (stat & (UCFE | UCOE | UCPE | UCBRK)) {
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/* some error which we do not handle, just do a pseudo read to reset the
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* status register */
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(void)data;
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}
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else {
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ctx_rx_cb(ctx_isr_arg, data);
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}
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__exit_isr();
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}
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