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https://github.com/RIOT-OS/RIOT.git
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278d39153d
- enabled hwrng feature - fixed 48MHz clock selection for the STM32L4
184 lines
5.8 KiB
C
184 lines
5.8 KiB
C
/*
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* Copyright (C) 2017 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32l4
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* @{
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*
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* @file
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* @brief Implementation of the CPU initialization
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
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* @}
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*/
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#include <stdint.h>
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#include "cpu.h"
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#include "irq.h"
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#include "periph_conf.h"
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#include "periph/init.h"
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/* make sure we have all needed information about the clock configuration */
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#ifndef CLOCK_HSE
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#error "Please provide CLOCK_HSE in your board's perhip_conf.h"
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#endif
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#ifndef CLOCK_LSE
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#error "Please provide CLOCK_LSE in your board's periph_conf.h"
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#endif
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#if !defined(CLOCK_PLL_M) || !defined(CLOCK_PLL_N) || !defined(CLOCK_PLL_R)
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#error "Please provide the PLL configuration in your board's periph_conf.h"
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#endif
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/**
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* @name PLL configuration
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* @{
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*/
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/* figure out which input to use */
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#if (CLOCK_HSE)
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#define PLL_IN CLOCK_HSE
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_HSE
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#else
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#define PLL_IN (48000000) /* MSI @ 48MHz */
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#define PLL_SRC RCC_PLLCFGR_PLLSRC_MSI
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#endif
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/**check configuration and get the corresponding bitfields */
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#if (CLOCK_PLL_M < 1 || CLOCK_PLL_M > 8)
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#error "PLL configuration: PLL M value is out of range"
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#endif
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#define PLL_M ((CLOCK_PLL_M - 1) << RCC_PLLCFGR_PLLM_Pos)
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#if (CLOCK_PLL_N < 8 || CLOCK_PLL_N > 86)
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#error "PLL configuration: PLL N value is out of range"
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#endif
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#define PLL_N (CLOCK_PLL_N << RCC_PLLCFGR_PLLN_Pos)
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#if (CLOCK_PLL_R == 2)
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#define PLL_R (0)
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#elif (CLOCK_PLL_R == 4)
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#define PLL_R (RCC_PLLCFGR_PLLR_0)
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#elif (CLOCK_PLL_R == 6)
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#define PLL_R (RCC_PLLCFGR_PLLR_1)
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#elif (CLOCK_PLL_R == 8)
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#define PLL_R (RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1)
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#else
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#error "PLL configuration: PLL R value is invalid"
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#endif
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/** @} */
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/**
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* @name Deduct the needed flash wait states from the core clock frequency
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* @{
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*/
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#if (CLOCK_CORECLOCK <= 16000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_0WS
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#elif (CLOCK_CORECLOCK <= 32000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_1WS
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#elif (CLOCK_CORECLOCK <= 48000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_2WS
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#elif (CLOCK_CORECLOCK <= 64000000)
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_3WS
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#else
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#define FLASH_WAITSTATES FLASH_ACR_LATENCY_4WS
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#endif
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/** @} */
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/**
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* @brief Configure the STM32L4's clock system
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*
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* We use the following configuration:
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* - we always enable the 32kHz low speed clock (LSI or LSE)
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* - we configure the MSI clock to 48MHz (for USB and RNG) and enable it
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* - if LSE present, we use it to stabilize the 48MHz MSI clock (MSIPLLEN)
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* - use either MSI @ 48MHz or HSE (4 to 48MHZ) as base clock
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* - we use the PLL as main clock provider
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* - we don't enable any ASI clock
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*
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* For the computation of the PLL configuration, see defines above.
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*/
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static void cpu_clock_init(void)
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{
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/* disable any interrupts. Global interrupts could be enabled if this is
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* called from some kind of bootloader... */
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unsigned is = irq_disable();
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RCC->CIER = 0;
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/* for the duration of the configuration, we fall-back to the maximum number
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* of flash wait states */
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FLASH->ACR = (FLASH_ACR_LATENCY_4WS);
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/* reset clock to MSI with 48MHz, disables all other clocks */
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RCC->CR = (RCC_CR_MSIRANGE_11 | RCC_CR_MSION | RCC_CR_MSIRGSEL);
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while (!(RCC->CR & RCC_CR_MSIRDY)) {}
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/* use MSI as system clock while we do any further configuration and
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* configure the AHB and APB clock dividers as configure by the board */
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RCC->CFGR = (RCC_CFGR_SW_MSI | CLOCK_AHB_DIV |
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CLOCK_APB1_DIV | CLOCK_APB2_DIV);
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_MSI) {}
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/* configure the low speed clock domain (LSE vs LSI) */
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#if CLOCK_LSE
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/* allow write access to backup domain */
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periph_clk_en(APB1, RCC_APB1ENR1_PWREN);
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PWR->CR1 |= PWR_CR1_DBP;
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/* enable LSE */
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RCC->BDCR = RCC_BDCR_LSEON;
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while (!(RCC->BDCR & RCC_BDCR_LSERDY)) {}
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/* disable write access to back domain when done */
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PWR->CR1 &= ~(PWR_CR1_DBP);
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periph_clk_dis(APB1, RCC_APB1ENR1_PWREN);
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/* now we can enable the MSI PLL mode */
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RCC->CR |= RCC_CR_MSIPLLEN;
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while (!(RCC->CR & RCC_CR_MSIRDY)) {}
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#else
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RCC->CSR = RCC_CSR_LSION;
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while (!(RCC->CSR & RCC_CSR_LSIRDY)) {}
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#endif
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/* select the MSI clock for the 48MHz clock tree (USB, RNG) */
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RCC->CCIPR = (RCC_CCIPR_CLK48SEL_0 | RCC_CCIPR_CLK48SEL_1);
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/* if configured: enable the HSE clock */
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#if CLOCK_HSE
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RCC->CR |= RCC_CR_HSEON;
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while (!(RCC->CR & RCC_CR_HSERDY)) {}
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#endif
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/* next we configure and enable the PLL */
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RCC->PLLCFGR = (PLL_SRC | PLL_M | PLL_N | PLL_R | RCC_PLLCFGR_PLLREN);
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RCC->CR |= RCC_CR_PLLON;
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while (!(RCC->CR & RCC_CR_PLLRDY)) {}
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/* now tell the system to use the PLL as main clock */
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RCC->CFGR |= RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL) {}
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/* finally we enable I+D cashes, pre-fetch, and we set the actual number of
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* needed flash wait states */
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FLASH->ACR = (FLASH_ACR_ICEN | FLASH_ACR_DCEN |
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FLASH_ACR_PRFTEN | FLASH_WAITSTATES);
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irq_restore(is);
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}
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/**
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* @brief Initialize the CPU, set IRQ priorities
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*/
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void cpu_init(void)
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{
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/* initialize the Cortex-M core */
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cortexm_init();
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/* initialize the clock system */
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cpu_clock_init();
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/* trigger static peripheral initialization */
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periph_init();
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}
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