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RIOT/tests/periph/gpio_ll/Makefile
Marian Buschsieweke 84800fdb5d
tests/periph/gpio_ll: Use better default pin config
The default pin config is only a place holder anyway. But if it is
invalid at least on AVR most of the firmware is considered unreachable.
This updates the default GPIO config to something that should look
plausible to the compiler for all MCUs supporting GPIO LL, so that
ROM and RAM size in the CI start making sense.
2024-01-21 08:38:47 +01:00

57 lines
1.5 KiB
Makefile

BOARD ?= nucleo-f767zi
# Custom per-board pin configuration (e.g. for setting PORT_IN, PIN_IN_0, ...)
# can be provided in a Makefile.$(BOARD) file:
-include Makefile.$(BOARD)
# Choose two input pins and two pins that do not conflict with stdio. All four
# *can* be on the same GPIO port, but the two output pins and the two inputs
# pins *must* be on the same port, respectively. Connect the first input to the
# first output pin and the second input pin to the second output pin, e.g. using
# jumper wires.
PORT_IN ?= 1
PORT_OUT ?= 1
PIN_IN_0 ?= 0
PIN_IN_1 ?= 1
PIN_OUT_0 ?= 2
PIN_OUT_1 ?= 3
# Boards that require tweaking for low ROM
LOW_ROM_BOARDS := \
nucleo-l011k4 \
stm32f030f4-demo \
#
ifneq (,$(filter $(BOARD),$(LOW_ROM_BOARDS)))
LOW_ROM ?= 1
endif
LOW_ROM ?= 0
include ../Makefile.periph_common
FEATURES_REQUIRED += periph_gpio_ll
FEATURES_OPTIONAL += periph_gpio_ll_irq
FEATURES_OPTIONAL += periph_gpio_ll_irq_level_triggered_high
FEATURES_OPTIONAL += periph_gpio_ll_irq_level_triggered_low
USEMODULE += ztimer_usec
include $(RIOTBASE)/Makefile.include
CFLAGS += -DPORT_OUT=$(PORT_OUT)
CFLAGS += -DPORT_IN=$(PORT_IN)
CFLAGS += -DPIN_IN_0=$(PIN_IN_0)
CFLAGS += -DPIN_IN_1=$(PIN_IN_1)
CFLAGS += -DPIN_OUT_0=$(PIN_OUT_0)
CFLAGS += -DPIN_OUT_1=$(PIN_OUT_1)
CFLAGS += -DLOW_ROM=$(LOW_ROM)
ifneq ($(MCU),esp32)
# We only need 1 thread (+ the Idle thread on some platforms) and we really
# want this app working on all boards.
CFLAGS += -DMAXTHREADS=2
else
# ESP32x SoCs uses an extra thread for esp_timer
CFLAGS += -DMAXTHREADS=3
endif