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222 lines
6.6 KiB
C
222 lines
6.6 KiB
C
/*
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* Copyright (C) 2016 Kaspar Schleiser <kaspar@schleiser.de>
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* 2015 Freie Universität Berlin
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* 2015 Engineering-Spirit
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* 2017-2019 OTA keys S.A.
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* 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @ingroup drivers_periph_pm
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* @{
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*
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* @file
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* @brief Implementation of the kernels power management interface
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*
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* @author Nick v. IJzendoorn <nijzndoorn@engineering-spirit.nl>
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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* @author Fabian Nack <nack@inf.fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*
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* @}
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*/
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#include "irq.h"
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#include "periph/pm.h"
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#include "periph/cpu_pm.h"
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#include "stmclk.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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#ifndef PM_STOP_CONFIG
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/**
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* @brief Define config flags for stop mode
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*
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* Available values can be found in reference manual, PWR section, register CR.
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*/
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#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F3) || \
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defined(CPU_FAM_STM32F1)
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#define PM_STOP_CONFIG (PWR_CR_LPDS)
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#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
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/* Enable ultra low-power and clear wakeup flags */
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#define PM_STOP_CONFIG (PWR_CR_LPSDSR | PWR_CR_ULP | PWR_CR_CWUF)
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#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32G4) || \
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defined(CPU_FAM_STM32L5)
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#define PM_STOP_CONFIG (PWR_CR1_LPMS_STOP1)
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#elif defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G0) || \
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defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
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#define PM_STOP_CONFIG (PWR_CR1_LPMS_0)
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#elif defined(CPU_FAM_STM32F7)
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#define PM_STOP_CONFIG (PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS)
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#elif defined(CPU_FAM_STM32MP1)
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#define PM_STOP_CONFIG (0)
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#elif defined(CPU_FAM_STM32U5)
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#define PM_STOP_CONFIG (0)
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#else
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#define PM_STOP_CONFIG (PWR_CR_LPDS | PWR_CR_FPDS)
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#endif
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#endif
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#ifndef PM_STANDBY_CONFIG
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/**
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* @brief Define config flags for standby mode
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*
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* Available values can be found in reference manual, PWR section, register CR.
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*/
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#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
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#define PM_STANDBY_CONFIG (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF | PWR_CR_ULP)
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#elif defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32G4) || \
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defined(CPU_FAM_STM32L5)
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#define PM_STANDBY_CONFIG (PWR_CR1_LPMS_STANDBY)
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#elif defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G0) || \
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defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
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#define PM_STANDBY_CONFIG (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)
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#elif defined(CPU_FAM_STM32F7)
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#define PM_STANDBY_CONFIG (PWR_CR1_PDDS | PWR_CR1_CSBF)
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#elif defined(CPU_FAM_STM32MP1)
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#define PM_STANDBY_CONFIG (0)
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#elif defined(CPU_FAM_STM32U5)
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#define PM_STANDBY_CONFIG (0)
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#else
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#define PM_STANDBY_CONFIG (PWR_CR_PDDS | PWR_CR_CWUF | PWR_CR_CSBF)
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#endif
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#endif
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#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
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defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
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defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
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defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
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#define PWR_CR_REG PWR->CR1
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#define PWR_WUP_REG PWR->CR3
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/* Allow overridable SRAM2 retention mode using CFLAGS */
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#ifndef STM32L4_SRAM2_RETENTION
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/* Disable SRAM2 retention by default for maximum power saving */
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#define STM32L4_SRAM2_RETENTION (0)
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#endif
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#elif defined(CPU_FAM_STM32F7)
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#define PWR_CR_REG PWR->CR1
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#define PWR_WUP_REG PWR->CSR2
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#elif defined(CPU_FAM_STM32MP1)
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#define PWR_CR_REG PWR->CR1
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#define PWR_WUP_REG PWR->MCUWKUPENR
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#else
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#define PWR_CR_REG PWR->CR
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#define PWR_WUP_REG PWR->CSR
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#endif
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void pm_set(unsigned mode)
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{
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int deep;
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switch (mode) {
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#if !defined(CPU_FAM_STM32MP1)
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case STM32_PM_STANDBY:
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PWR_CR_REG &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG);
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PWR_CR_REG |= PM_STANDBY_CONFIG;
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#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
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defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32L5) || \
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defined(CPU_FAM_STM32WL)
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#if STM32L4_SRAM2_RETENTION
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PWR->CR3 |= PWR_CR3_RRS;
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#else
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PWR->CR3 &= ~PWR_CR3_RRS;
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#endif
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#endif
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#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32G4) || \
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defined(CPU_FAM_STM32L5)
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/* Clear flags */
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PWR->SCR |= PWR_SCR_CSBF;
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#endif
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/* Enable WKUP pin to use for wakeup from standby mode */
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PWR_WUP_REG |= PM_EWUP_CONFIG;
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/* Set SLEEPDEEP bit of system control block */
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deep = 1;
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pm_backup_regulator_on();
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break;
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#endif
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case STM32_PM_STOP:
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PWR_CR_REG &= ~(PM_STOP_CONFIG | PM_STANDBY_CONFIG);
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PWR_CR_REG |= PM_STOP_CONFIG;
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/* Set SLEEPDEEP bit of system control block */
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deep = 1;
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break;
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default:
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deep = 0;
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break;
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}
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cortexm_sleep(deep);
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if (deep) {
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/* Re-init clock after STOP */
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#if !defined(CPU_FAM_STM32MP1) || IS_USED(MODULE_STM32MP1_ENG_MODE)
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stmclk_init_sysclk();
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#endif
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}
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}
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/**
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* @name Registers and related configuration bits to retain
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* the backup domain registers, using the backup regulator
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* @{
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*/
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#if defined(PWR_CSR1_BRE)
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#define PWR_BACKUP_REGULATOR_REG PWR->CSR1
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#define BKPREG_CONFIG (PWR_CSR1_BRE | PWR_CSR1_EIWUP)
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#define BKPREG_READY (PWR_CSR1_BRR)
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#elif defined(PWR_CSR_BRE)
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#define PWR_BACKUP_REGULATOR_REG PWR->CSR
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#define BKPREG_CONFIG (PWR_CSR_BRE)
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#define BKPREG_READY (PWR_CSR_BRR)
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#elif defined(PWR_CR2_BREN)
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#define PWR_BACKUP_REGULATOR_REG PWR->CR2
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#define BKPREG_CONFIG (PWR_CR2_BREN)
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#define BKPREG_READY (PWR_CR2_BRRDY)
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#endif
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/** @} */
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bool pm_backup_regulator_is_on(void)
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{
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#if defined(PWR_BACKUP_REGULATOR_REG)
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return (PWR_BACKUP_REGULATOR_REG & BKPREG_READY) == BKPREG_READY;
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#else
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return false;
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#endif
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}
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void pm_backup_regulator_on(void)
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{
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#if defined(PWR_BACKUP_REGULATOR_REG)
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bool locked = stmclk_dbp_is_locked();
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if (locked) {
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stmclk_dbp_unlock();
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}
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PWR_BACKUP_REGULATOR_REG |= BKPREG_CONFIG;
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while (!(PWR_BACKUP_REGULATOR_REG & BKPREG_READY)){}
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if (locked) {
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stmclk_dbp_lock();
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}
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#endif
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}
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void pm_backup_regulator_off(void)
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{
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#if defined(PWR_BACKUP_REGULATOR_REG)
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bool locked = stmclk_dbp_is_locked();
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if (locked) {
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stmclk_dbp_unlock();
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}
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PWR_BACKUP_REGULATOR_REG &= ~BKPREG_CONFIG;
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if (locked) {
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stmclk_dbp_lock();
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}
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#endif
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}
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