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107 lines
3.2 KiB
C
107 lines
3.2 KiB
C
/*
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* Copyright (C) 2018 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Low-level flash lock/unlock implementation
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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* @author Oleg Artamonov <oleg@unwds.com>
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*
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* @}
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*/
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#include "cpu.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1)
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/* Data EEPROM and control register unlock keys */
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#define FLASH_KEY1 ((uint32_t)0x89ABCDEF)
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#define FLASH_KEY2 ((uint32_t)0x02030405)
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#define CNTRL_REG (FLASH->PECR)
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#define CNTRL_REG_LOCK (FLASH_PECR_PELOCK)
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#define KEY_REG (FLASH->PEKEYR)
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#elif defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5)
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#define FLASH_KEY1 ((uint32_t)0x45670123)
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#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
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#define CNTRL_REG (FLASH->NSCR)
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#if defined(CPU_FAM_STM32U5)
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#define CNTRL_REG_LOCK (FLASH_NSCR_LOCK)
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#define KEY_REG (FLASH->NSKEYR)
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#define FLASH_SR_EOP (FLASH_NSSR_EOP)
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#else
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#define CNTRL_REG_LOCK (FLASH_NSCR_NSLOCK)
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#define KEY_REG (FLASH->NSKEYR)
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#define FLASH_SR_EOP (FLASH_NSSR_NSEOP)
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#endif
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#else
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#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
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defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
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defined(CPU_FAM_STM32F2) || defined(CPU_FAM_STM32F4) || \
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defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32WL) || \
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defined(CPU_FAM_STM32C0)
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#define FLASH_KEY1 ((uint32_t)0x45670123)
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#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
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#endif
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#define CNTRL_REG (FLASH->CR)
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#define CNTRL_REG_LOCK (FLASH_CR_LOCK)
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#define KEY_REG (FLASH->KEYR)
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#endif
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#if defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32C0)
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#define FLASH_SR_BSY (FLASH_SR_BSY1)
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#endif
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#if defined(CPU_FAM_STM32L5)
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#define FLASH_SR_BSY (FLASH_NSSR_NSBSY)
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#define FLASH_SR_REG (FLASH->NSSR)
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#elif defined(CPU_FAM_STM32U5)
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#define FLASH_SR_BSY (FLASH_NSSR_BSY)
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#define FLASH_SR_REG (FLASH->NSSR)
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#else
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#define FLASH_SR_REG (FLASH->SR)
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#endif
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void _unlock(void)
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{
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if (CNTRL_REG & CNTRL_REG_LOCK) {
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DEBUG("[flash-common] unlocking the flash module\n");
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KEY_REG = FLASH_KEY1;
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KEY_REG = FLASH_KEY2;
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}
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}
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void _lock(void)
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{
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if (!(CNTRL_REG & CNTRL_REG_LOCK)) {
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DEBUG("[flash-common] locking the flash module\n");
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CNTRL_REG |= CNTRL_REG_LOCK;
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}
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}
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void _wait_for_pending_operations(void)
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{
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if (FLASH_SR_REG & FLASH_SR_BSY) {
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DEBUG("[flash-common] waiting for any pending operation to finish\n");
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while (FLASH_SR_REG & FLASH_SR_BSY) {}
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}
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/* Clear 'end of operation' bit in status register, for other STM32 boards
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this bit is set only if EOPIE is set, which is currently not done */
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#if defined(CPU_FAM_STM32F0) || defined(CPU_FAM_STM32F1) || \
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defined(CPU_FAM_STM32F3) || defined(CPU_FAM_STM32L0) || \
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defined(CPU_FAM_STM32L1)
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FLASH_SR_REG |= FLASH_SR_EOP;
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#endif
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}
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