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99 lines
2.7 KiB
C
99 lines
2.7 KiB
C
/*
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* Copyright (C) 2021 Mesotic SAS
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_nrf9160
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* @{
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*
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* @file
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* @brief nRF9160 interrupt vector definitions
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*
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* @author Dylan Laduranty <dylan.laduranty@mesotic.com>
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*
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* @}
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*/
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#include <stdint.h>
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#include "cpu.h"
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#include "vectors_cortexm.h"
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/* define a local dummy handler as it needs to be in the same compilation unit
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* as the alias definition */
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void dummy_handler(void) {
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dummy_handler_default();
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}
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/* nRF9160 specific interrupt vectors */
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WEAK_DEFAULT void isr_spu(void);
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WEAK_DEFAULT void isr_clock_power(void);
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WEAK_DEFAULT void isr_uarte0_spim0_spis0_twim0_twis0(void);
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WEAK_DEFAULT void isr_uarte1_spim1_spis1_twim1_twis1(void);
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WEAK_DEFAULT void isr_uarte2_spim2_spis2_twim2_twis2(void);
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WEAK_DEFAULT void isr_uarte3_spim3_spis3_twim3_twis3(void);
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WEAK_DEFAULT void isr_gpiote0(void);
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WEAK_DEFAULT void isr_saadc(void);
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WEAK_DEFAULT void isr_timer0(void);
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WEAK_DEFAULT void isr_timer1(void);
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WEAK_DEFAULT void isr_timer2(void);
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WEAK_DEFAULT void isr_rtc0(void);
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WEAK_DEFAULT void isr_rtc1(void);
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WEAK_DEFAULT void isr_wdt(void);
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WEAK_DEFAULT void isr_egu0(void);
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WEAK_DEFAULT void isr_egu1(void);
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WEAK_DEFAULT void isr_egu2(void);
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WEAK_DEFAULT void isr_egu3(void);
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WEAK_DEFAULT void isr_egu4(void);
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WEAK_DEFAULT void isr_egu5(void);
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WEAK_DEFAULT void isr_pwm0(void);
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WEAK_DEFAULT void isr_pwm1(void);
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WEAK_DEFAULT void isr_pwm2(void);
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WEAK_DEFAULT void isr_pwm3(void);
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WEAK_DEFAULT void isr_pdm(void);
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WEAK_DEFAULT void isr_i2s(void);
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WEAK_DEFAULT void isr_ipc(void);
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WEAK_DEFAULT void isr_fpu(void);
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WEAK_DEFAULT void isr_gpiote1(void);
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WEAK_DEFAULT void isr_kmu(void);
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WEAK_DEFAULT void isr_cryptocell(void);
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/* CPU specific interrupt vector table */
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ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
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[3] = isr_spu, /* SPU */
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[5] = isr_clock_power, /* power_clock */
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[8] = isr_uarte0_spim0_spis0_twim0_twis0,
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[9] = isr_uarte1_spim1_spis1_twim1_twis1,
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[10] = isr_uarte2_spim2_spis2_twim2_twis2,
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[11] = isr_uarte3_spim3_spis3_twim3_twis3,
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[13] = isr_gpiote0, /* gpiote0 */
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[14] = isr_saadc,
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[15] = isr_timer0,
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[16] = isr_timer1,
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[17] = isr_timer2,
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[20] = isr_rtc0,
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[21] = isr_rtc1,
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[24] = isr_wdt,
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[27] = isr_egu0,
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[28] = isr_egu1,
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[29] = isr_egu2,
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[30] = isr_egu3,
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[31] = isr_egu4,
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[32] = isr_egu5,
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[33] = isr_pwm0,
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[34] = isr_pwm1,
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[35] = isr_pwm2,
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[36] = isr_pwm3,
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[38] = isr_pdm,
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[40] = isr_i2s,
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[42] = isr_ipc,
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[44] = isr_fpu,
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[49] = isr_gpiote1,
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[57] = isr_kmu,
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[64] = isr_cryptocell
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};
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