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RIOT supports two distinct families of the MSP430: The [MSP430 x1xx]
MCU family and the [MSP430 F2xx/G2xx] MCU family. For both incompatible
MCU families the code was located in the msp430fxyz folder, resulting
in case of the UART driver in particularly bizarre code looking roughly
like this:
#ifndef UART_USE_USCI
/* implementation of x1xx peripheral ... */
#else
/* implementation of F2xx/G2xx peripheral ... */
#endif
/* zero shared code between both variants */
This splits the peripheral drivers for USCI and USART serial IP blocks
into separate files and relocates everything in cpu/msp430, similar to
how cpu/stm32 is organized.
[MSP430 x1xx]: https://www.ti.com/lit/ug/slau049f/slau049f.pdf
[MSP430 F2xx/G2xx]: https://www.ti.com/lit/ug/slau144k/slau144k.pdf
101 lines
2.5 KiB
C
101 lines
2.5 KiB
C
/*
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* Copyright (C) 2013, Freie Universitaet Berlin (FUB). All rights reserved.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_msp430
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* @{
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*
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* @file
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* @brief Common CPU definitions for MSP430
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*
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*/
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief This arch uses the inlined IRQ API.
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*/
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#define IRQ_API_INLINED (1)
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/**
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* @name Configure the internal flash memory
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* @{
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*/
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#define FLASHPAGE_SIZE (512U)
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#if defined (CPU_MODEL_MSP430F1611)
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#define CPU_FLASH_BASE (0x4000)
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#define FLASHPAGE_NUMOF (96U) /* 48K */
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#elif defined (CPU_MODEL_MSP430F1612)
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#define CPU_FLASH_BASE (0x2600) /* first sector is only 256 byte, skip it*/
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#define FLASHPAGE_NUMOF (109U) /* 54.5K */
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#elif defined (CPU_MODEL_MSP430F2617)
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#define CPU_FLASH_BASE (0x3200) /* first sector is only 256 byte, skip it*/
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#define FLASHPAGE_NUMOF (103U) /* we can currently only access 51.5K */
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#elif defined (CPU_MODEL_MSP430F2618)
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#define CPU_FLASH_BASE (0x3200) /* first sector is only 256 byte, skip it*/
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#define FLASHPAGE_NUMOF (103U) /* we can currently only access 51.5K */
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#elif defined (CPU_MODEL_CC430F6137)
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#define CPU_FLASH_BASE (0x8000)
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#define FLASHPAGE_NUMOF (64U) /* 32K */
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#endif
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/* The minimum block size which can be written is 1B. However, the erase
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* block is always FLASHPAGE_SIZE.
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*/
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#define FLASHPAGE_WRITE_BLOCK_SIZE (1U)
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/* Writing should be always 2 byte aligned */
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#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (2U)
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/** @} */
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/**
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* @name Kernel configuration
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* @{
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*/
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#ifndef THREAD_EXTRA_STACKSIZE_PRINTF
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# define THREAD_EXTRA_STACKSIZE_PRINTF (256)
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#endif
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#ifndef THREAD_EXTRA_STACKSIZE_PRINTF
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# define THREAD_EXTRA_STACKSIZE_PRINTF_FLOAT (THREAD_EXTRA_STACKSIZE_PRINTF)
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#endif
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#ifndef THREAD_STACKSIZE_DEFAULT
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# define THREAD_STACKSIZE_DEFAULT (384)
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#endif
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#ifndef THREAD_STACKSIZE_IDLE
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# define THREAD_STACKSIZE_IDLE (96)
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#endif
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#ifndef ISR_STACKSIZE
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# define ISR_STACKSIZE (256)
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#endif
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#ifndef CONFIG_GNRC_PKTBUF_SIZE
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/* TODO: Make this value overall MTU dependent */
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# define CONFIG_GNRC_PKTBUF_SIZE (2560)
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#endif
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#ifndef GNRC_IPV6_STACK_SIZE
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# define GNRC_IPV6_STACK_SIZE (512)
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_CONF_H */
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/** @} */
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