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168 lines
5.4 KiB
C
168 lines
5.4 KiB
C
/*
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* Copyright (C) 2017 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_kinetis
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* @brief CPU specific implementations for the NXP Kinetis K series of
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* Cortex-M MCUs
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* @{
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*
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* @file
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* @brief Implementation specific CPU configuration options
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef CPU_CONF_KINETIS_K_H
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#define CPU_CONF_KINETIS_K_H
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#if (KINETIS_FAMILY == 2)
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#if (KINETIS_SUBFAMILY == 2)
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/* Kinetis K22 */
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#if defined(CPU_MODEL_MK22FX512VLH12) || \
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defined(CPU_MODEL_MK22FN1M0VLH12) || \
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defined(CPU_MODEL_MK22FX512VLK12) || \
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defined(CPU_MODEL_MK22FN1M0VLK12) || \
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defined(CPU_MODEL_MK22FX512VLL12) || \
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defined(CPU_MODEL_MK22FN1M0VLL12) || \
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defined(CPU_MODEL_MK22FX512VLQ12) || \
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defined(CPU_MODEL_MK22FN1M0VLQ12) || \
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defined(CPU_MODEL_MK22FX512VMC12) || \
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defined(CPU_MODEL_MK22FN1M0VMC12) || \
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defined(CPU_MODEL_MK22FX512VMD12) || \
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defined(CPU_MODEL_MK22FN1M0VMD12)
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#include "vendor/MK22F12.h"
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#elif defined(CPU_MODEL_MK22FN128VDC10) || \
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defined(CPU_MODEL_MK22FN128VLH10) || \
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defined(CPU_MODEL_MK22FN128VLL10) || \
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defined(CPU_MODEL_MK22FN128VMP10)
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#include "vendor/MK22F12810.h"
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#elif defined(CPU_MODEL_MK22FN128CAH12) || \
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defined(CPU_MODEL_MK22FN256CAH12) || \
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defined(CPU_MODEL_MK22FN256VDC12) || \
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defined(CPU_MODEL_MK22FN256VLH12) || \
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defined(CPU_MODEL_MK22FN256VLL12) || \
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defined(CPU_MODEL_MK22FN256VMP12)
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#include "vendor/MK22F25612.h"
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#elif defined(CPU_MODEL_MK22FN512CAP12) || \
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defined(CPU_MODEL_MK22FN512VDC12) || \
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defined(CPU_MODEL_MK22FN512VFX12) || \
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defined(CPU_MODEL_MK22FN512VLH12) || \
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defined(CPU_MODEL_MK22FN512VLL12) || \
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defined(CPU_MODEL_MK22FN512VMP12)
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#include "vendor/MK22F51212.h"
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#elif defined(CPU_MODEL_MK22FN1M0AVLH12) || \
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defined(CPU_MODEL_MK22FN1M0AVLK12) || \
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defined(CPU_MODEL_MK22FN1M0AVLL12) || \
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defined(CPU_MODEL_MK22FN1M0AVLQ12) || \
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defined(CPU_MODEL_MK22FN1M0AVMC12) || \
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defined(CPU_MODEL_MK22FN1M0AVMD12) || \
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defined(CPU_MODEL_MK22FX512AVLH12) || \
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defined(CPU_MODEL_MK22FX512AVLK12) || \
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defined(CPU_MODEL_MK22FX512AVLL12) || \
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defined(CPU_MODEL_MK22FX512AVLQ12) || \
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defined(CPU_MODEL_MK22FX512AVMC12) || \
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defined(CPU_MODEL_MK22FX512AVMD12)
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#include "vendor/MK22FA12.h"
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#endif
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#elif (KINETIS_SUBFAMILY == 0)
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#if defined(CPU_MODEL_MK20DX64VLH7) || \
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defined(CPU_MODEL_MK20DX128VLH7) || \
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defined(CPU_MODEL_MK20DX256VLH7) || \
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defined(CPU_MODEL_MK20DX64VLK7) || \
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defined(CPU_MODEL_MK20DX128VLK7) || \
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defined(CPU_MODEL_MK20DX256VLK7) || \
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defined(CPU_MODEL_MK20DX128VLL7) || \
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defined(CPU_MODEL_MK20DX256VLL7) || \
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defined(CPU_MODEL_MK20DX64VMB7) || \
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defined(CPU_MODEL_MK20DX128VMB7) || \
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defined(CPU_MODEL_MK20DX256VMB7) || \
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defined(CPU_MODEL_MK20DX128VML7) || \
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defined(CPU_MODEL_MK20DX256VML7)
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#include "vendor/MK20D7.h"
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#endif
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#endif /* (KINETIS_SUBFAMILY == y) */
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#elif (KINETIS_FAMILY == 6)
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#if (KINETIS_SUBFAMILY == 0)
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#if defined(CPU_MODEL_MK60DN256VLL10) || \
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defined(CPU_MODEL_MK60DN256VLQ10) || \
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defined(CPU_MODEL_MK60DN256VMC10) || \
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defined(CPU_MODEL_MK60DN256VMD10) || \
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defined(CPU_MODEL_MK60DN512VLL10) || \
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defined(CPU_MODEL_MK60DN512VLQ10) || \
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defined(CPU_MODEL_MK60DN512VMC10) || \
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defined(CPU_MODEL_MK60DN512VMD10) || \
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defined(CPU_MODEL_MK60DX256VLL10) || \
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defined(CPU_MODEL_MK60DX256VLQ10) || \
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defined(CPU_MODEL_MK60DX256VMC10) || \
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defined(CPU_MODEL_MK60DX256VMD10)
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#include "vendor/MK60D10.h"
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#endif
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/**
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* @brief This CPU provides an additional ADC clock divider as CFG1[ADICLK]=1
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*/
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#define KINETIS_HAVE_ADICLK_BUS_DIV_2 1
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#elif (KINETIS_SUBFAMILY == 4)
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#if defined(CPU_MODEL_MK64FN1M0CAJ12) || \
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defined(CPU_MODEL_MK64FN1M0VDC12) || \
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defined(CPU_MODEL_MK64FN1M0VLL12) || \
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defined(CPU_MODEL_MK64FN1M0VLQ12) || \
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defined(CPU_MODEL_MK64FN1M0VMD12) || \
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defined(CPU_MODEL_MK64FX512VDC12) || \
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defined(CPU_MODEL_MK64FX512VLL12) || \
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defined(CPU_MODEL_MK64FX512VLQ12) || \
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defined(CPU_MODEL_MK64FX512VMD12)
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#include "vendor/MK64F12.h"
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/**
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* @name Hardware random number generator module configuration
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*
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* For K64F SCG3 or SCG6 can be used depending on if the the
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* peripheral is accessed through AIPS-lite0 or AIPS-lite1.
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* For K64F RNGA is only mapped to SCG6.
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* @{
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*/
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#define HWRNG_CLK_REG (SIM->SCGC6)
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#define HWRNG_CLK_REG_SHIFT (SIM_SCGC6_RNGA_SHIFT)
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/** @} */
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#endif
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#endif /* (KINETIS_SUBFAMILY == y) */
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#endif /* (KINETIS_FAMILY == x) */
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/**
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* @name Flashpage configuration
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* @{
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*/
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#define FLASHPAGE_SIZE (4096U)
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#define FLASHPAGE_NUMOF ((KINETIS_ROMSIZE * 1024) / FLASHPAGE_SIZE)
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/* The minimum block size which can be written is 8B (Phrase). However, the
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* erase block is always FLASHPAGE_SIZE.
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*/
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#define FLASHPAGE_BLOCK_PHRASE (8U)
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#define FLASHPAGE_WRITE_BLOCK_SIZE FLASHPAGE_BLOCK_PHRASE
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/* Writing should be always 8 bytes aligned */
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#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT FLASHPAGE_BLOCK_PHRASE
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/* Section erase and programming must be 16 bytes aligned */
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#define FLASHPAGE_BLOCK_SECTION_ALIGNMENT (16U)
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/** @} */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_CONF_KINETIS_K_H */
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/** @} */
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