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7d1d5e77d8
New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
25 lines
643 B
C
25 lines
643 B
C
// See LICENSE for license details.
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#ifndef _SIFIVE_GPIO_H
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#define _SIFIVE_GPIO_H
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#define GPIO_INPUT_VAL (0x00)
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#define GPIO_INPUT_EN (0x04)
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#define GPIO_OUTPUT_EN (0x08)
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#define GPIO_OUTPUT_VAL (0x0C)
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#define GPIO_PULLUP_EN (0x10)
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#define GPIO_DRIVE (0x14)
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#define GPIO_RISE_IE (0x18)
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#define GPIO_RISE_IP (0x1C)
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#define GPIO_FALL_IE (0x20)
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#define GPIO_FALL_IP (0x24)
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#define GPIO_HIGH_IE (0x28)
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#define GPIO_HIGH_IP (0x2C)
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#define GPIO_LOW_IE (0x30)
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#define GPIO_LOW_IP (0x34)
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#define GPIO_IOF_EN (0x38)
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#define GPIO_IOF_SEL (0x3C)
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#define GPIO_OUTPUT_XOR (0x40)
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#endif /* _SIFIVE_GPIO_H */
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