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https://github.com/RIOT-OS/RIOT.git
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482 lines
15 KiB
C
482 lines
15 KiB
C
/*
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* Copyright (C) 2016 Leon George
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* Copyright (C) 2018 Anton Gerasimov
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_cc26x2_cc13x2_definitions
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* @{
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*
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* @file
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* @brief CC26x2, CC13x2 AUX register definitions
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*/
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#ifndef CC26X2_CC13X2_AUX_H
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#define CC26X2_CC13X2_AUX_H
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#include <stdbool.h>
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#include "cc26xx_cc13xx.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief AUX_AIODIO registers
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*/
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typedef struct {
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reg32_t IOMODE; /**< Input output mode */
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reg32_t GPIODIE; /**< GPIO data input enable */
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reg32_t IOPOE; /**< I/O peripheral output enable */
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reg32_t GPIODOUT; /**< GPIO data output */
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reg32_t GPIODIN; /**< GPIO data input */
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reg32_t GPIODOUTSET; /**< GPIO data out set */
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reg32_t GPIODOUTCLR; /**< GPIO data out clear */
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reg32_t GPIODOUTTGL; /**< GPIO data out toggle */
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reg32_t IO0PSEL; /**< I/O 0 peripheral select */
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reg32_t IO1PSEL; /**< I/O 1 peripheral select */
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reg32_t IO2PSEL; /**< I/O 2 peripheral select */
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reg32_t IO3PSEL; /**< I/O 3 peripheral select */
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reg32_t IO4PSEL; /**< I/O 4 peripheral select */
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reg32_t IO5PSEL; /**< I/O 5 peripheral select */
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reg32_t IO6PSEL; /**< I/O 6 peripheral select */
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reg32_t IO7PSEL; /**< I/O 7 peripheral select */
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reg32_t IOMODEH; /**< Input output mode high */
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reg32_t IOMODEL; /**< Input output mode low */
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} aux_aiodio_regs_t;
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @brief AUX_AIODIO0 base address
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*/
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#define AUX_AIODIO0_BASE (PERIPH_BASE + 0xCC000)
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/**
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* @brief AUX_AIODIO1 base address
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*/
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#define AUX_AIODIO1_BASE (PERIPH_BASE + 0xCD000)
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/**
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* @brief AUX_AIODIO2 base address
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*/
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#define AUX_AIODIO2_BASE (PERIPH_BASE + 0xCE000)
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/**
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* @brief AUX_AIODIO3 base address
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*/
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#define AUX_AIODIO3_BASE (PERIPH_BASE + 0xCF000)
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/** @} */
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/**
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* @brief AUX_AIODIO0 register bank
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*/
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#define AUX_AIODIO0 ((aux_aiodio_regs_t *) (AUX_AIODIO0_BASE))
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/**
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* @brief AUX_AIODIO1 register bank
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*/
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#define AUX_AIODIO1 ((aux_aiodio_regs_t *) (AUX_AIODIO1_BASE))
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/**
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* @brief AUX_AIODIO2 register bank
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*/
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#define AUX_AIODIO2 ((aux_aiodio_regs_t *) (AUX_AIODIO2_BASE))
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/**
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* @brief AUX_AIODIO3 register bank
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*/
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#define AUX_AIODIO3 ((aux_aiodio_regs_t *) (AUX_AIODIO3_BASE))
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/**
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* @brief AUX_TDC registers
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*/
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typedef struct {
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reg32_t CTL; /**< Control */
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reg32_t STAT; /**< Status */
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reg32_t RESULT; /**< Result */
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reg32_t SATCFG; /**< Saturaion configuration */
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reg32_t TRIGSRC; /**< Trigger source */
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reg32_t TRIGCNT; /**< Trigger counter */
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reg32_t TRIGCNTLOAD; /**< Trigger counter load */
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reg32_t TRIGCNTCFG; /**< Trigger counter config */
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reg32_t PRECTL; /**< Prescaler control */
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reg32_t PRECNTR; /**< Prescaler counter */
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} aux_tdc_regs_t;
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @brief AUX_TDC base address
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*/
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#define AUX_TDC_BASE (PERIPH_BASE + 0xC4000)
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/** @} */
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/**
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* @brief AUX_TDC register bank
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*/
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#define AUX_TDC ((aux_tdc_regs_t *) (AUX_TDC_BASE))
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/**
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* @brief AUX_EVCTL registers
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*/
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typedef struct {
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reg32_t EVSTAT0; /**< Event Status 0 */
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reg32_t EVSTAT1; /**< Event Status 1 */
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reg32_t EVSTAT2; /**< Event Status 2 */
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reg32_t EVSTAT3; /**< Event Status 3 */
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reg32_t SCEWEVCFG0; /**< Sensor Controller Engine Wait Event Configuration 0 */
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reg32_t SCEWEVCFG1; /**< Sensor Controller Engine Wait Event Configuration 1 */
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reg32_t DMACTL; /**< Direct Memory Access Control */
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reg32_t __reserved1; /**< Reserved */
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reg32_t SWEVSET; /**< Software Event Set */
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reg32_t EVTOAONFLAGS; /**< Events To AON Flags */
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reg32_t EVTOAONPOL; /**< Events To AON Polarity */
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reg32_t EVTOAONFLAGSCLR; /**< Events To AON Clear */
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reg32_t EVTOMCUFLAGS; /**< Events to MCU Flags */
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reg32_t EVTOMCUPOL; /**< Event To MCU Polarity */
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reg32_t EVTOMCUFLAGSCLR; /**< Events To MCU Flags Clear */
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reg32_t COMBEVTOMCUMASK; /**< Combined Event To MCU Mask */
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reg32_t EVOBSCFG; /**< Event Observation Configuration */
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reg32_t PROGDLY; /**< Programmable Delay */
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reg32_t MANUAL; /**< Manual */
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reg32_t EVSTAT0L; /**< Event Status 0 Low */
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reg32_t EVSTAT0H; /**< Event Status 0 High */
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reg32_t EVSTAT1L; /**< Event Status 1 Low */
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reg32_t EVSTAT1H; /**< Event Status 1 High */
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reg32_t EVSTAT2L; /**< Event Status 2 Low */
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reg32_t EVSTAT2H; /**< Event Status 2 High */
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reg32_t EVSTAT3L; /**< Event Status 3 Low */
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reg32_t EVSTAT3H; /**< Event Status 3 High */
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} aux_evctl_regs_t;
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @brief AUX_EVCTL base address
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*/
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#define AUX_EVCTL_BASE (PERIPH_BASE + 0xC5000)
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/** @} */
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/**
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* @brief AUX_EVCTL register bank
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*/
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#define AUX_EVCTL ((aux_evctl_regs_t *) (AUX_EVCTL_BASE))
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/**
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* @brief AUX_SYSIF registers
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*/
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typedef struct {
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reg32_t OPMODEREQ; /**< Operational Mode Request */
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reg32_t OPMODEACK; /**< Operational Mode Acknowledgement */
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reg32_t PROGWU0CFG; /**< Programmable Wakeup 0 Configuration */
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reg32_t PROGWU1CFG; /**< Programmable Wakeup 1 Configuration */
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reg32_t PROGWU2CFG; /**< Programmable Wakeup 2 Configuration */
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reg32_t PROGWU3CFG; /**< Programmable Wakeup 3 Configuration */
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reg32_t SWWUTRIG; /**< Software Wakeup Triggers */
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reg32_t WUFLAGS; /**< Wakeup Flags */
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reg32_t WUFLAGSCLR; /**< Wakeup Flags Clear */
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reg32_t WUGATE; /**< Wakeup Gate */
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reg32_t VECCFG0; /**< Vector Configuration 0 */
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reg32_t VECCFG1; /**< Vector Configuration 1 */
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reg32_t VECCFG2; /**< Vector Configuration 2 */
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reg32_t VECCFG3; /**< Vector Configuration 3 */
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reg32_t VECCFG4; /**< Vector Configuration 4 */
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reg32_t VECCFG5; /**< Vector Configuration 5 */
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reg32_t VECCFG6; /**< Vector Configuration 6 */
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reg32_t VECCFG7; /**< Vector Configuration 7 */
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reg32_t EVSYNCRATE; /**< Event Synchronization Rate */
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reg32_t PEROPRATE; /**< Peripheral Operational Rate */
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reg32_t ADCCLKCTL; /**< ADC Clock Control */
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reg32_t TDCCLKCTL; /**< TDC Counter Clock Control */
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reg32_t TDCREFCLKCTL; /**< TDC Reference Clock Control */
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reg32_t TIMER2CLKCTL; /**< AUX_TIMER2 Clock Control */
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reg32_t TIMER2CLKSTAT; /**< AUX_TIMER2 Clock Status */
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reg32_t TIMER2CLKSWITCH; /**< AUX_TIMER2 Clock Switch */
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reg32_t TIMER2DBGCTL; /**< AUX_TIMER2 Debug Control */
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reg32_t __reserved1; /**< Reserved */
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reg32_t CLKSHIFTDET; /**< Clock Shift Detection */
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reg32_t RECHARGETRIG; /**< VDDR Recharge Trigger */
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reg32_t RECHARGEDET; /**< VDDR Recharge Detection */
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reg32_t RTCSUBSECINC0; /**< Real Time Counter Sub Second Increment 0 */
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reg32_t RTCSUBSECINC1; /**< Real Time Counter Sub Second Increment 1 */
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reg32_t RTCSUBSECINCCTL; /**< Real Time Counter Sub Second Increment Control */
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reg32_t RTCSEC; /**< Real Time Counter Second */
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reg32_t RTCSUBSEC; /**< Real Time Counter Sub-Second */
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reg32_t RTCEVCLR; /**< AON_RTC Event Clear */
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reg32_t BATMONBAT; /**< AON_BATMON Battery Voltage Value */
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reg32_t __reserved2; /**< Reserved */
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reg32_t BATMONTEMP; /**< AON_BATMON Temperature Value */
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reg32_t TIMERHALT; /**< Timer Halt */
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reg32_t __reserved3[0x3]; /**< Reserved */
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reg32_t TIMER2BRIDGE; /**< AUX_TIMER2 Bridge */
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reg32_t SWPWRPROF; /**< Software Power Profiler */
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} aux_sysif_regs_t;
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/**
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* @brief AUX_SYSIF register values
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* @{
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*/
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#define AUX_SYSIF_OPMODEREQ_REQ_PDLP 0x00000003
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#define AUX_SYSIF_OPMODEREQ_REQ_PDA 0x00000002
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#define AUX_SYSIF_OPMODEREQ_REQ_LP 0x00000001
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#define AUX_SYSIF_OPMODEREQ_REQ_A 0x00000000
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/** @} */
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @brief AUX_SYSIF base address
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*/
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#define AUX_SYSIF_BASE (PERIPH_BASE + 0xC6000)
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/** @} */
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/**
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* @brief AUX_SYSIF register bank
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*/
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#define AUX_SYSIF ((aux_sysif_regs_t *) (AUX_SYSIF_BASE))
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/**
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* @brief AUX_SYSIF functions
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* @{
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*/
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/**
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* @brief Changes the AUX operational mode
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*
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* @note Only this function should be used to change the operational mode,
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* because it needs to be done in order.
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*
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* @param[in] target_opmode The opmode we want to change to.
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*/
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void aux_sysif_opmode_change(uint32_t target_opmode);
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/** @} */
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/**
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* @brief AUX_TIMER01 registers
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*/
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typedef struct {
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reg32_t T0CFG; /**< Timer 0 Configuration */
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reg32_t T0CTL; /**< Timer 0 Control */
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reg32_t T0TARGET; /**< Timer 0 Target */
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reg32_t T0CNTR; /**< Timer 0 Counter */
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reg32_t T1CFG; /**< Timer 1 Configuration */
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reg32_t T1TARGET; /**< Timer 1 Target */
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reg32_t T1CTL; /**< Timer 1 Control */
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reg32_t T1CNTR; /**< Timer 0 Counter */
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} aux_timer01_regs_t;
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @brief AUX_TIMER01 base address
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*/
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#define AUX_TIMER01_BASE (PERIPH_BASE + 0xC7000)
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/** @} */
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/**
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* @brief AUX_TIMER01 register bank
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*/
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#define AUX_TIMER01 ((aux_timer01_regs_t *) (AUX_TIMER01_BASE))
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/**
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* @brief AUX_TIMER2 registers
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*/
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typedef struct {
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reg32_t CTL; /**< Timer 2 Control */
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reg32_t TARGET; /**< Timer 2 Target */
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reg32_t SHDWTARGET; /**< Timer 2 Shadow Target */
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reg32_t CNTR; /**< Timer 2 Counter */
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reg32_t PRECFG; /**< Timer 2 Prescaler Config */
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reg32_t EVCTL; /**< Timer 2 Event Control */
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reg32_t PULSETRIG; /**< Timer 2 Pulse Trigger */
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reg32_t __reserved1[0x19]; /**< Reserved */
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reg32_t CH0EVCFG; /**< Timer 2 Channel 0 Event Configuration */
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reg32_t CH0CCFG; /**< Timer 2 Channel 0 Capture Configuration */
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reg32_t CH0PCC; /**< Timer 2 Channel 0 Pipeline Capture Compare */
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reg32_t CH0CC; /**< Timer 2 Channel 0 Capture Compare */
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reg32_t CH1EVCFG; /**< Timer 2 Channel 1 Event Configuration */
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reg32_t CH1CCFG; /**< Timer 2 Channel 1 Capture Configuration */
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reg32_t CH1PCC; /**< Timer 2 Channel 1 Pipeline Capture Compare */
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reg32_t CH1CC; /**< Timer 2 Channel 1 Capture Compare */
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reg32_t CH2EVCFG; /**< Timer 2 Channel 2 Event Configuration */
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reg32_t CH2CCFG; /**< Timer 2 Channel 2 Capture Configuration */
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reg32_t CH2PCC; /**< Timer 2 Channel 2 Pipeline Capture Compare */
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reg32_t CH2CC; /**< Timer 2 Channel 2 Capture Compare */
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reg32_t CH3EVCFG; /**< Timer 2 Channel 3 Event Configuration */
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reg32_t CH3CCFG; /**< Timer 2 Channel 3 Capture Configuration */
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reg32_t CH3PCC; /**< Timer 2 Channel 3 Pipeline Capture Compare */
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reg32_t CH3CC; /**< Timer 2 Channel 3 Capture Compare */
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} aux_timer2_regs_t;
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @brief AUX_TIMER2 base address
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*/
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#define AUX_TIMER2_BASE (PERIPH_BASE + 0xC3000)
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/** @} */
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/**
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* @brief AUX_TIMER2 register bank
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*/
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#define AUX_TIMER2 ((aux_timer2_regs_t *) (AUX_TIMER2_BASE))
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/**
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* @brief AUX_SMPH registers
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*/
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typedef struct {
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reg32_t SMPH0; /**< Semaphore 0 */
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reg32_t SMPH1; /**< Semaphore 1 */
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reg32_t SMPH2; /**< Semaphore 2 */
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reg32_t SMPH3; /**< Semaphore 3 */
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reg32_t SMPH4; /**< Semaphore 4 */
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reg32_t SMPH5; /**< Semaphore 5 */
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reg32_t SMPH6; /**< Semaphore 6 */
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reg32_t SMPH7; /**< Semaphore 7 */
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reg32_t AUTOTAKE; /**< Sticky Request For Single Semaphore */
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} aux_smph_regs_t;
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @brief AUX_SMPH base address
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*/
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#define AUX_SMPH_BASE (PERIPH_BASE + 0xC8000)
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/** @} */
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/**
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* @brief AUX_SMPH register bank
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*/
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#define AUX_SMPH ((aux_smph_regs_t *) (AUX_SMPH_BASE))
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/**
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* @brief AUX_ANAIF registers
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*/
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typedef struct {
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reg32_t __reserved1[0x4]; /**< Reserved */
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reg32_t ADCCTL; /**< ADC Control */
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reg32_t ADCFIFOSTAT; /**< ADC FIFO status */
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reg32_t ADCFIFO; /**< ADC FIFO */
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reg32_t ADCTRIG; /**< ADC Trigger */
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reg32_t ISRCCTL; /**< Current Source Control */
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reg32_t __reserved2[0x3]; /**< Reserved */
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reg32_t DACCTL; /**< DAC Control */
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reg32_t LPMBIASCTL; /**< Low-Power Mode Bias Control */
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reg32_t DACSMPLCTL; /**< DAC Sample Control */
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reg32_t DACSMPLCFG0; /**< DAC Sample Configuration 0 */
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reg32_t DACSMPLCFG1; /**< DAC Sample Configuration 1 */
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reg32_t DACVALUE; /**< DAC Value */
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reg32_t DACSTAT; /**< DAC Status */
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} aux_anaif_regs_t;
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @brief AUX_ANAIF base address
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*/
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#define AUX_ANAIF_BASE (PERIPH_BASE + 0xC9000)
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/** @} */
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/**
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* @brief AUX_ANAIF register bank
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*/
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#define AUX_ANAIF ((aux_anaif_regs_t *) (AUX_ANAIF_BASE))
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/**
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* @brief ADI_4_AUX registers
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*/
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typedef struct {
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reg8_t MUX0; /**< Multiplexer 0 */
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reg8_t MUX1; /**< Multiplexer 1 */
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reg8_t MUX2; /**< Multiplexer 2 */
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reg8_t MUX3; /**< Multiplexer 3 */
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reg8_t ISRC; /**< Current Source */
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reg8_t COMP; /**< Comparator */
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reg8_t MUX4; /**< Multiplexer 4 */
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reg8_t ADC0; /**< ADC Control 0 */
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reg8_t ADC1; /**< ADC Control 1 */
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reg8_t ADCREF0; /**< ADC Reference 0 */
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reg8_t ADCREF1; /**< ADC Reference 1 */
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reg8_t __reserved1[0x3]; /**< Reserved */
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reg8_t LPMBIAS; /**< Internal */
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} adi_4_aux_regs_t;
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/**
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* @brief ADI_4_AUX registers using masked 8-bit access
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*/
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typedef struct {
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reg8_m8_t MUX0; /**< Multiplexer 0 */
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reg8_m8_t MUX1; /**< Multiplexer 1 */
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reg8_m8_t MUX2; /**< Multiplexer 2 */
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reg8_m8_t MUX3; /**< Multiplexer 3 */
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reg8_m8_t ISRC; /**< Current Source */
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reg8_m8_t COMP; /**< Comparator */
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reg8_m8_t MUX4; /**< Multiplexer 4 */
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reg8_m8_t ADC0; /**< ADC Control 0 */
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reg8_m8_t ADC1; /**< ADC Control 1 */
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reg8_m8_t ADCREF0; /**< ADC Reference 0 */
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reg8_m8_t ADCREF1; /**< ADC Reference 1 */
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reg8_m8_t __reserved1[0x3]; /**< Reserved */
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reg8_m8_t LPMBIAS; /**< Internal */
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} adi_4_aux_regs_m8_t;
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/**
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* @brief ADI_4_AUX register values
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* @{
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*/
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#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_m 0x00000038
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#define ADI_4_AUX_COMP_LPM_BIAS_WIDTH_TRIM_s 3
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#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_m 0x0000003F
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#define ADI_4_AUX_LPMBIAS_LPM_TRIM_IOUT_s 0
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/** @} */
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @brief ADI_4_AUX base address
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*/
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#define ADI_4_AUX_BASE (PERIPH_BASE + 0xCB000)
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/**
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* @brief ADI_4_AUX base address for masked 8-bit access
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*/
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#define ADI_4_AUX_BASE_M8 (ADI_4_AUX_BASE + ADI_MASK8B)
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/** @} */
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/**
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* @brief ADI_4_AUX register bank
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*/
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#define ADI_4_AUX ((adi_4_aux_regs_t *) (ADI_4_AUX_BASE))
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/**
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* @brief ADI_4_AUX register bank
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*/
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#define ADI_4_AUX_M8 ((adi_4_aux_regs_m8_t *) (ADI_4_AUX_BASE_M8))
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/**
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* @brief Semamphore used for ADDI
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*/
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#define ADDI_SEM AUX_SMPH->SMPH0
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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#endif /* CC26X2_CC13X2_AUX_H */
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/** @}*/
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