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https://github.com/RIOT-OS/RIOT.git
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166 lines
4.5 KiB
C
166 lines
4.5 KiB
C
/*
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* Copyright (C) 2015 Loci Controls Inc.
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* 2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc2538
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* @ingroup drivers_periph_spi
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* @{
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*
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* @file
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* @brief Low-level SPI driver implementation
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*
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* @author Ian Martin <ian@locicontrols.com>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include <assert.h>
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#include "vendor/hw_memmap.h"
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#include "vendor/hw_ssi.h"
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#include "cpu.h"
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#include "mutex.h"
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#include "periph/spi.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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/**
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* @brief Array holding one pre-initialized mutex for each SPI device
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*/
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static mutex_t locks[SPI_NUMOF];
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static inline cc2538_ssi_t *dev(spi_t bus)
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{
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/* .num is either 0 or 1, return respective base address */
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return (spi_config[bus].num) ? (cc2538_ssi_t *)SSI1_BASE : (cc2538_ssi_t *)SSI0_BASE;
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}
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static inline void poweron(spi_t bus)
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{
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SYS_CTRL_RCGCSSI |= (1 << spi_config[bus].num);
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SYS_CTRL_SCGCSSI |= (1 << spi_config[bus].num);
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SYS_CTRL_DCGCSSI |= (1 << spi_config[bus].num);
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}
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static inline void poweroff(spi_t bus)
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{
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SYS_CTRL_RCGCSSI &= ~(1 << spi_config[bus].num);
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SYS_CTRL_SCGCSSI &= ~(1 << spi_config[bus].num);
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SYS_CTRL_DCGCSSI &= ~(1 << spi_config[bus].num);
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}
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void spi_init(spi_t bus)
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{
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DEBUG("%s: bus=%u\n", __FUNCTION__, bus);
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assert(bus < SPI_NUMOF);
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/* init mutex for given bus */
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mutex_init(&locks[bus]);
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/* temporarily power on the device */
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poweron(bus);
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/* configure device to be a master and disable SSI operation mode */
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dev(bus)->CR1 = 0;
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/* configure system clock as SSI clock source */
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dev(bus)->CC = SSI_CC_CS_IODIV;
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/* and power off the bus again */
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poweroff(bus);
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/* trigger SPI pin configuration */
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spi_init_pins(bus);
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}
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void spi_init_pins(spi_t bus)
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{
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DEBUG("%s: bus=%u\n", __FUNCTION__, bus);
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/* select values according to SPI device */
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cc2538_ioc_sel_t txd = spi_config[bus].num ? SSI1_TXD : SSI0_TXD;
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cc2538_ioc_sel_t clk = spi_config[bus].num ? SSI1_CLK_OUT : SSI0_CLK_OUT;
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cc2538_ioc_sel_t fss = spi_config[bus].num ? SSI1_FSS_OUT : SSI0_FSS_OUT;
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cc2538_ioc_pin_t rxd = spi_config[bus].num ? SSI1_RXD : SSI0_RXD;
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/* init pin functions and multiplexing */
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gpio_init_mux(spi_config[bus].mosi_pin, OVERRIDE_ENABLE, txd, GPIO_MUX_NONE);
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gpio_init_mux(spi_config[bus].sck_pin, OVERRIDE_ENABLE, clk, GPIO_MUX_NONE);
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gpio_init_mux(spi_config[bus].cs_pin, OVERRIDE_ENABLE, fss, GPIO_MUX_NONE);
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gpio_init_mux(spi_config[bus].miso_pin, OVERRIDE_DISABLE, GPIO_MUX_NONE, rxd);
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}
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void spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
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{
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assert((unsigned)bus < SPI_NUMOF);
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DEBUG("%s: bus=%u\n", __FUNCTION__, bus);
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(void)cs;
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/* lock the bus */
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mutex_lock(&locks[bus]);
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/* power on device */
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poweron(bus);
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/* configure SCR clock field, data-width and mode */
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dev(bus)->CR0 = 0;
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dev(bus)->CPSR = (spi_clk_config[clk].cpsr);
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dev(bus)->CR0 = ((spi_clk_config[clk].scr << 8) | mode | SSI_CR0_DSS(8));
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/* enable SSI device */
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dev(bus)->CR1 = SSI_CR1_SSE;
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}
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void spi_release(spi_t bus)
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{
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DEBUG("%s: bus=%u\n", __FUNCTION__, bus);
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/* disable and power off device */
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dev(bus)->CR1 = 0;
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poweroff(bus);
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/* and release lock... */
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mutex_unlock(&locks[bus]);
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}
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static uint8_t _trx(cc2538_ssi_t *dev, uint8_t in)
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{
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while (!(dev->SR & SSI_SR_TNF)) {}
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dev->DR = in;
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while (!(dev->SR & SSI_SR_RNE)) {}
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return dev->DR;
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}
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void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
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const void *out, void *in, size_t len)
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{
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DEBUG("%s: bus=%u, len=%u\n", __FUNCTION__, bus, (unsigned)len);
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const uint8_t *out_buf = out;
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uint8_t *in_buf = in;
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assert(out_buf || in_buf);
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if (cs != SPI_CS_UNDEF) {
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gpio_clear((gpio_t)cs);
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}
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if (!in_buf) {
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for (const void *end = out_buf + len; out_buf != end; ++out_buf) {
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_trx(dev(bus), *out_buf);
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}
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}
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else if (!out_buf) {
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for (void *end = in_buf + len; in_buf != end; ++in_buf) {
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*in_buf = _trx(dev(bus), 0);
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}
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}
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else {
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for (void *end = in_buf + len; in_buf != end; ++in_buf, ++out_buf) {
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*in_buf = _trx(dev(bus), *out_buf);
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}
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}
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if ((!cont) && (cs != SPI_CS_UNDEF)) {
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gpio_set((gpio_t)cs);
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}
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}
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