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82 lines
2.3 KiB
C
82 lines
2.3 KiB
C
/*
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* Copyright (C) 2020 ML!PA Consulting GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc2538
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* @ingroup drivers_periph_pm
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* @{
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*
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* @file
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* @brief Implementation of the kernels power management interface
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*
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* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
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*
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* @}
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*/
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#include "vendor/hw_nvic.h"
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#include "periph/pm.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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void pm_set(unsigned mode)
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{
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bool deep = false;
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bool switch_osc = false;
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switch (mode) {
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case 0:
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/* lowest 16k RAM are lost here, wake by GPIO */
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SYS_CTRL_PMCTL = 0x3;
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deep = true;
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break;
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case 1:
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/* lowest 16k RAM are lost here, wake by GPIO & RTT */
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SYS_CTRL_PMCTL = 0x2;
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deep = true;
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break;
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case 2:
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/* all memory retained, wake by GPIO, RTT & USB */
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SYS_CTRL_PMCTL = 0x1;
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deep = true;
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break;
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case 3:
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/* all memory retained, wake by any interrupt source */
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deep = true;
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SYS_CTRL_PMCTL = 0x0;
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break;
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}
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if (deep) {
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*(cc2538_reg_t*) NVIC_SYS_CTRL |= NVIC_SYS_CTRL_SLEEPDEEP;
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/* If we used the 32 MHz clock, we have to switch to 16 MHz for deep sleep */
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switch_osc = !SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC;
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/* set to 0 in order to ensure that the 32 MHz XOSC is started as quick
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as possible after power mode */
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SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC_PD = 0;
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}
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/* switch to 16 MHz clock */
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if (switch_osc) {
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SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC = 1;
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while (!SYS_CTRL->cc2538_sys_ctrl_clk_sta.CLOCK_STAbits.OSC) {}
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}
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cortexm_sleep(deep);
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/* switch back to 32 MHz clock */
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if (switch_osc) {
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SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC = 0;
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/* Power down the oscillator not selected by OSC bit */
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SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC_PD = 1;
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while (SYS_CTRL->cc2538_sys_ctrl_clk_sta.CLOCK_STAbits.OSC) {}
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}
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}
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