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https://github.com/RIOT-OS/RIOT.git
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100 lines
3.1 KiB
C
100 lines
3.1 KiB
C
/*
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* Copyright (C) 2014 Loci Controls Inc.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_cc2538
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* @{
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*
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* @file
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* @brief Implementation of the CPU initialization
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*
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* @author Ian Martin <ian@locicontrols.com>
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* @}
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*/
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#include "stdio_base.h"
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#include "cpu.h"
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#include "kernel_init.h"
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#include "periph/init.h"
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#include "periph_conf.h"
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static void cpu_clock_init(void);
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/**
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* @brief Initialize the CPU, set IRQ priorities
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*/
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void cpu_init(void)
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{
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/* initialize the Cortex-M core */
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cortexm_init();
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/* Enable the CC2538's more compact alternate interrupt mapping */
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SYS_CTRL->I_MAP = 1;
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/* initialize the clock system */
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cpu_clock_init();
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/* initialize stdio prior to periph_init() to allow use of DEBUG() there */
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early_init();
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/* trigger static peripheral initialization */
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periph_init();
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}
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/**
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* @brief Configure the controllers clock system
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*/
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static void cpu_clock_init(void)
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{
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#if SYS_CTRL_OSC32K_USE_XTAL
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/* set the XOSC32K_Q pads to analog for the external crystal: */
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gpio_software_control(GPIO_PD6);
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gpio_dir_input(GPIO_PD6);
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IOC_PXX_OVER[GPIO_PD6] = IOC_OVERRIDE_ANA;
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gpio_software_control(GPIO_PD7);
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gpio_dir_input(GPIO_PD7);
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IOC_PXX_OVER[GPIO_PD7] = IOC_OVERRIDE_ANA;
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#endif
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/* CLOCK_CTRL.OSC32K register bit can be written at any time, but only takes
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effect when 16MHz RCOSC is the active system clock source, 16MHz RCOSC is
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the active clock on reset but to be idempotent make sure it's the
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selected source clock */
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SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC = 1;
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while (SYS_CTRL->cc2538_sys_ctrl_clk_sta.CLOCK_STAbits.SOURCE_CHANGE) {}
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#if SYS_CTRL_OSC32K_USE_XTAL
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SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC32K = 0;
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while (SYS_CTRL->cc2538_sys_ctrl_clk_sta.CLOCK_STAbits.OSC32K) {}
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#else
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SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC32K = 1;
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while (!SYS_CTRL->cc2538_sys_ctrl_clk_sta.CLOCK_STAbits.OSC32K) {}
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#endif
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#if SYS_CTRL_OSC_USE_XTAL
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SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC = 0;
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#else
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SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC = 1;
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#endif
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/* power down the oscillator not selected by OSC bit */
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SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.OSC_PD = 1;
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/* set desired system clock rate */
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SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.SYS_DIV = \
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__builtin_ctz(XOSC32M_FREQ / CLOCK_CORECLOCK);
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/* set desired I/O clock rate */
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SYS_CTRL->cc2538_sys_ctrl_clk_ctrl.CLOCK_CTRLbits.IO_DIV = \
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__builtin_ctz(XOSC32M_FREQ / CLOCK_IO);
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/* wait for new clock settings to take effect */
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while (SYS_CTRL->cc2538_sys_ctrl_clk_sta.CLOCK_STAbits.SOURCE_CHANGE) {}
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#if SYS_CTRL_OSC32K_USE_XTAL
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/* 32-kHz crystal oscillator to stabilize after a positive transition */
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while (SYS_CTRL->cc2538_sys_ctrl_clk_sta.CLOCK_STAbits.SYNC_32K) {}
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while (!SYS_CTRL->cc2538_sys_ctrl_clk_sta.CLOCK_STAbits.SYNC_32K) {}
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#endif
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}
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