mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
c2c2cc8592
Since https://github.com/RIOT-OS/RIOT/pull/20935 gpio_write() uses a `bool` instead of an `int`. This does the same treatment for `gpio_read()`. This does indeed add an instruction to `gpio_read()` implementations. However, users caring about an instruction more are better served with `gpio_ll_read()` anyway. And `gpio_read() == 1` is often seen in newcomer's code, which would now work as expected.
448 lines
11 KiB
C
448 lines
11 KiB
C
/*
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* Copyright (C) 2021-2023 Gerson Fernando Budke <nandojve@gmail.com>
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_atxmega
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* @ingroup cpu_atxmega_periph
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* @{
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*
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* @file
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* @brief Low-level GPIO driver implementation
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*
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* @author Gerson Fernando Budke <nandojve@gmail.com>
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*
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* @}
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*/
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#include <avr/interrupt.h>
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#include <stdio.h>
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#include "bitarithm.h"
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#include "cpu.h"
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#include "irq.h"
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#include "periph/gpio.h"
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#include "periph_conf.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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/**
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* @brief GPIO port base
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*
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* GPIO_PORT_BASE resides in the IO address space and must be 16 bits.
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*/
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#define GPIO_PORT_BASE ((uint16_t)&PORTA)
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/**
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* @brief GPIO port structure offset
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*
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* The PORT_t struct it is not complete filled and it is necessary define the
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* address offset manually.
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*/
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#define GPIO_PORT_OFFSET (0x20)
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static gpio_isr_ctx_t config_ctx[GPIO_EXT_INT_NUMOF];
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static uint8_t config_irq[GPIO_EXT_INT_NUMOF];
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/**
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* @brief Extract the pin number of the given pin
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*/
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static inline uint8_t _pin_mask(gpio_t pin)
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{
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return (pin & 0xff);
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}
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/**
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* @brief Extract the port number of the given pin
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*/
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static inline uint8_t _port_num(gpio_t pin)
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{
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return (pin >> 8) & 0x0f;
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}
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/**
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* @brief Generate the PORTx address of the give pin in the IO address space
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*/
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static inline PORT_t *_port_addr(gpio_t pin)
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{
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uint8_t port_num = _port_num(pin);
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uint16_t port_addr = GPIO_PORT_BASE + (port_num * GPIO_PORT_OFFSET);
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return (PORT_t *) port_addr;
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}
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static inline void _print_config(gpio_t pin)
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{
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PORT_t *port = _port_addr(pin);
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uint8_t pin_mask = _pin_mask(pin);
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volatile uint8_t *pin_ctrl = &port->PIN0CTRL;
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DEBUG("PORT: 0x%04x, PIN: 0x%02x\n", (uint16_t)port, pin_mask);
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DEBUG("DIR: 0x%02x, IN: 0x%02x, OUT: 0x%02x\n", port->DIR, port->IN, port->OUT);
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DEBUG("INTCTRL: 0x%02x\nINTFLAGS: 0x%02x\n", port->INTCTRL, port->INTFLAGS);
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DEBUG("INT0MASK: 0x%02x\nINT1MASK: 0x%02x\n", port->INT0MASK, port->INT1MASK);
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for (uint8_t p = 0; p < 8; p++) {
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DEBUG("PIN%dCTRL: 0x%02x\n", p, pin_ctrl[p]);
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}
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}
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static inline void _gpio_pinctrl_set(gpio_t pin, gpio_mode_t mode,
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gpio_flank_t flank, gpio_cb_t cb,
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void *arg)
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{
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uint8_t pin_mask = _pin_mask(pin);
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uint8_t port_num = _port_num(pin);
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PORT_t *port = _port_addr(pin);
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volatile uint8_t *pin_ctrl = &port->PIN0CTRL;
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uint8_t irq_state;
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uint8_t in_sense_cfg;
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uint8_t pins;
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uint8_t pin_idx;
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in_sense_cfg = (mode & ~PORT_ISC_gm);
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in_sense_cfg |= (mode & GPIO_ANALOG)
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? PORT_ISC_INPUT_DISABLE_gc
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: ((flank >> 4) & PORT_ISC_gm);
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pins = pin_mask;
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pin_idx = 0;
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if (mode & GPIO_OUT) {
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port->DIRSET = pin_mask;
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}
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else {
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port->DIRCLR = pin_mask;
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}
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irq_state = irq_disable();
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while (pins) {
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pins = bitarithm_test_and_clear(pins, &pin_idx);
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pin_ctrl[pin_idx] = in_sense_cfg;
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}
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if (flank & GPIO_INT_DISABLED_ALL) {
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config_ctx[port_num + PORT_MAX].cb = NULL;
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config_ctx[port_num + PORT_MAX].arg = NULL;
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config_irq[port_num + PORT_MAX] = 0;
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config_ctx[port_num].cb = NULL;
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config_ctx[port_num].arg = NULL;
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config_irq[port_num] = 0;
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port->INTCTRL = 0;
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port->INT1MASK = 0;
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port->INT0MASK = 0;
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port->INTFLAGS = PORT_INT1IF_bm | PORT_INT0IF_bm;
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}
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else if (flank & GPIO_INT1_VCT) {
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config_ctx[port_num + PORT_MAX].cb = cb;
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config_ctx[port_num + PORT_MAX].arg = arg;
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config_irq[port_num + PORT_MAX] = (flank & GPIO_LVL_HIGH)
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<< PORT_INT1LVL_gp;
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if ((flank & GPIO_LVL_HIGH) == GPIO_LVL_OFF) {
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port->INT1MASK &= ~pin_mask;
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}
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else {
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port->INT1MASK |= pin_mask;
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}
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port->INTFLAGS = PORT_INT1IF_bm;
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/* Get mask from INT 0 and apply new INT 1 mask */
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port->INTCTRL = (port->INTCTRL & PORT_INT0LVL_gm)
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| config_irq[port_num + PORT_MAX];
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}
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else {
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config_ctx[port_num].cb = cb;
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config_ctx[port_num].arg = arg;
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config_irq[port_num] = (flank & GPIO_LVL_HIGH)
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<< PORT_INT0LVL_gp;
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if ((flank & GPIO_LVL_HIGH) == GPIO_LVL_OFF) {
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port->INT0MASK &= ~pin_mask;
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}
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else {
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port->INT0MASK |= pin_mask;
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}
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port->INTFLAGS = PORT_INT0IF_bm;
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/* Get mask from INT 1 and apply new INT 0 mask */
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port->INTCTRL = (port->INTCTRL & PORT_INT1LVL_gm)
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| config_irq[port_num];
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}
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irq_restore(irq_state);
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}
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int gpio_init(gpio_t pin, gpio_mode_t mode)
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{
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DEBUG("gpio_init pin = 0x%02x mode = 0x%02x\n", pin, mode);
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_gpio_pinctrl_set(pin, mode, GPIO_INT_DISABLED_ALL, NULL, NULL);
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return 0;
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}
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int gpio_init_int(gpio_t pin, gpio_mode_t mode, gpio_flank_t flank,
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gpio_cb_t cb, void *arg)
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{
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DEBUG("gpio_init_int pin = 0x%02x mode = 0x%02x flank = 0x%02x\n", pin,
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mode, flank);
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if (mode & GPIO_ANALOG) {
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DEBUG("Pin can't be ANALOG (input buffer disabled) and INT at same time.\n");
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return -1;
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}
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_gpio_pinctrl_set(pin, mode, flank, cb, arg);
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if (IS_ACTIVE(ENABLE_DEBUG)) {
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_print_config(pin);
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}
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return 0;
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}
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void gpio_irq_enable(gpio_t pin)
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{
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DEBUG("gpio_irq_enable pin = 0x%04x \n", pin);
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uint8_t pin_mask = _pin_mask(pin);
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uint8_t port_num = _port_num(pin);
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PORT_t *port = _port_addr(pin);
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if (port->INT1MASK & pin_mask) {
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port->INTFLAGS = PORT_INT1IF_bm;
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port->INTCTRL |= config_irq[port_num + PORT_MAX];
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}
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if (port->INT0MASK & pin_mask) {
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port->INTFLAGS = PORT_INT0IF_bm;
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port->INTCTRL |= config_irq[port_num];
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}
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if (IS_ACTIVE(ENABLE_DEBUG)) {
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_print_config(pin);
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}
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}
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void gpio_irq_disable(gpio_t pin)
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{
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DEBUG("gpio_irq_disable pin = 0x%04x \n", pin);
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uint8_t pin_mask = _pin_mask(pin);
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PORT_t *port = _port_addr(pin);
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if (port->INT1MASK & pin_mask) {
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port->INTCTRL &= ~PORT_INT1LVL_gm;
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}
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if (port->INT0MASK & pin_mask) {
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port->INTCTRL &= ~PORT_INT0LVL_gm;
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}
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if (IS_ACTIVE(ENABLE_DEBUG)) {
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_print_config(pin);
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}
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}
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bool gpio_read(gpio_t pin)
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{
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PORT_t *port = _port_addr(pin);
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uint8_t pin_mask = _pin_mask(pin);
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if (IS_ACTIVE(ENABLE_DEBUG)) {
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_print_config(pin);
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}
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return port->IN & pin_mask;
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}
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void gpio_set(gpio_t pin)
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{
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DEBUG("gpio_set pin = 0x%04x \n", pin);
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PORT_t *port = _port_addr(pin);
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uint8_t pin_mask = _pin_mask(pin);
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port->OUTSET = pin_mask;
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if (IS_ACTIVE(ENABLE_DEBUG)) {
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_print_config(pin);
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}
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}
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void gpio_clear(gpio_t pin)
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{
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DEBUG("gpio_clear pin = 0x%04x \n", pin);
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PORT_t *port = _port_addr(pin);
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uint8_t pin_mask = _pin_mask(pin);
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port->OUTCLR = pin_mask;
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if (IS_ACTIVE(ENABLE_DEBUG)) {
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_print_config(pin);
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}
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}
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void gpio_toggle(gpio_t pin)
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{
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DEBUG("gpio_toggle pin = 0x%04x \n", pin);
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PORT_t *port = _port_addr(pin);
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uint8_t pin_mask = _pin_mask(pin);
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port->OUTTGL = pin_mask;
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if (IS_ACTIVE(ENABLE_DEBUG)) {
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_print_config(pin);
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}
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}
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void gpio_write(gpio_t pin, bool value)
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{
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DEBUG("gpio_write pin = 0x%04x, value = 0x%02x \n", pin, value);
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if (value) {
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gpio_set(pin);
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}
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else {
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gpio_clear(pin);
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}
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}
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static inline void irq_handler(uint8_t port_num, uint8_t isr_vct_num)
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{
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DEBUG("irq_handler port = 0x%02x, vct_num = %d \n", port_num, isr_vct_num);
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if (isr_vct_num) {
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port_num += PORT_MAX;
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}
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if (config_ctx[port_num].cb) {
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config_ctx[port_num].cb(config_ctx[port_num].arg);
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}
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else {
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DEBUG("WARNING! irq_handler without callback\n");
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}
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}
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#if defined(PORTA_INT0_vect)
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AVR8_ISR(PORTA_INT0_vect, irq_handler, PORT_A, 0);
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#endif
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#if defined(PORTA_INT1_vect)
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AVR8_ISR(PORTA_INT1_vect, irq_handler, PORT_A, 1);
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#endif
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#if defined(PORTB_INT0_vect)
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AVR8_ISR(PORTB_INT0_vect, irq_handler, PORT_B, 0);
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#endif
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#if defined(PORTB_INT1_vect)
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AVR8_ISR(PORTB_INT1_vect, irq_handler, PORT_B, 1);
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#endif
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#if defined(PORTC_INT0_vect)
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AVR8_ISR(PORTC_INT0_vect, irq_handler, PORT_C, 0);
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#endif
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#if defined(PORTC_INT1_vect)
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AVR8_ISR(PORTC_INT1_vect, irq_handler, PORT_C, 1);
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#endif
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#if defined(PORTD_INT0_vect)
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AVR8_ISR(PORTD_INT0_vect, irq_handler, PORT_D, 0);
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#endif
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#if defined(PORTD_INT1_vect)
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AVR8_ISR(PORTD_INT1_vect, irq_handler, PORT_D, 1);
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#endif
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#if defined(PORTE_INT0_vect)
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AVR8_ISR(PORTE_INT0_vect, irq_handler, PORT_E, 0);
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#endif
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#if defined(PORTE_INT1_vect)
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AVR8_ISR(PORTE_INT1_vect, irq_handler, PORT_E, 1);
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#endif
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#if defined(PORTF_INT0_vect)
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AVR8_ISR(PORTF_INT0_vect, irq_handler, PORT_F, 0);
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#endif
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#if defined(PORTF_INT1_vect)
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AVR8_ISR(PORTF_INT1_vect, irq_handler, PORT_F, 1);
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#endif
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#if defined(PORTG_INT0_vect)
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AVR8_ISR(PORTG_INT0_vect, irq_handler, PORT_G, 0);
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#endif
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#if defined(PORTG_INT1_vect)
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AVR8_ISR(PORTG_INT1_vect, irq_handler, PORT_G, 1);
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#endif
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#if defined(PORTH_INT0_vect)
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AVR8_ISR(PORTH_INT0_vect, irq_handler, PORT_H, 0);
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#endif
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#if defined(PORTH_INT1_vect)
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AVR8_ISR(PORTH_INT1_vect, irq_handler, PORT_H, 1);
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#endif
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#if defined(PORTJ_INT0_vect)
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AVR8_ISR(PORTJ_INT0_vect, irq_handler, PORT_J, 0);
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#endif
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#if defined(PORTJ_INT1_vect)
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AVR8_ISR(PORTJ_INT1_vect, irq_handler, PORT_J, 1);
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#endif
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#if defined(PORTK_INT0_vect)
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AVR8_ISR(PORTK_INT0_vect, irq_handler, PORT_K, 0);
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#endif
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#if defined(PORTK_INT1_vect)
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AVR8_ISR(PORTK_INT1_vect, irq_handler, PORT_K, 1);
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#endif
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#if defined(PORTL_INT0_vect)
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AVR8_ISR(PORTL_INT0_vect, irq_handler, PORT_L, 0);
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#endif
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#if defined(PORTL_INT1_vect)
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AVR8_ISR(PORTL_INT1_vect, irq_handler, PORT_L, 1);
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#endif
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#if defined(PORTM_INT0_vect)
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AVR8_ISR(PORTM_INT0_vect, irq_handler, PORT_M, 0);
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#endif
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#if defined(PORTM_INT1_vect)
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AVR8_ISR(PORTM_INT1_vect, irq_handler, PORT_M, 1);
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#endif
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#if defined(PORTN_INT0_vect)
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AVR8_ISR(PORTN_INT0_vect, irq_handler, PORT_N, 0);
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#endif
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#if defined(PORTN_INT1_vect)
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AVR8_ISR(PORTN_INT1_vect, irq_handler, PORT_N, 1);
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#endif
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#if defined(PORTP_INT0_vect)
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AVR8_ISR(PORTP_INT0_vect, irq_handler, PORT_P, 0);
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#endif
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#if defined(PORTP_INT1_vect)
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AVR8_ISR(PORTP_INT1_vect, irq_handler, PORT_P, 1);
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#endif
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#if defined(PORTQ_INT0_vect)
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AVR8_ISR(PORTQ_INT0_vect, irq_handler, PORT_Q, 0);
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#endif
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#if defined(PORTQ_INT1_vect)
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AVR8_ISR(PORTQ_INT1_vect, irq_handler, PORT_Q, 1);
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#endif
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#if defined(PORTR_INT0_vect)
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AVR8_ISR(PORTR_INT0_vect, irq_handler, PORT_R, 0);
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#endif
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#if defined(PORTR_INT1_vect)
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AVR8_ISR(PORTR_INT1_vect, irq_handler, PORT_R, 1);
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#endif
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