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783afbc666
The current ISR implementation for AVR8 requires use of avr8_[enter/exit]_isr pair which add some boilerplate on code. This add AVR8_ISR which clean-up the code and make it simpler and hides any schedule detail from the user perspective. This is a preparation for future scheduling and irq optimizations. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
259 lines
6.9 KiB
C
259 lines
6.9 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin, Hinnerk van Bruinehsen
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* 2017 Thomas Perrot <thomas.perrot@tupi.fr>
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* 2023 Hugues Larrive
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* 2023 Gerson Fernando Budke
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_atmega_common
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* @ingroup drivers_periph_uart
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* @{
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*
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* @file
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* @brief Low-level UART driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Hinnerk van Bruinehsen <h.v.bruinehsen@fu-berlin.de>
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* @author Thomas Perrot <thomas.perrot@tupi.fr>
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* @author Hugues Larrive <hugues.larrive@pm.me>
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* @author Gerson Fernando Budke <nandojve@gmail.com>
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*
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*
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* Support static BAUD rate calculation using STDIO_UART_BAUDRATE.
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* Set STDIO_UART_BAUDRATE to the desired baud rate and pass it as a -D argument
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* at compilation time (e.g. in the boards Makefile.include file).
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* UART_BAUD_TOL can be set to guarantee a BAUD rate tolerance at compile time or
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* to switch to double speed transmission (U2X) to achieve a lower tolerance.
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* At runtime, this tolerance is not guaranteed to be met.
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* However, an error message will be displayed at compile time.
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*
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* @}
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*/
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#include "cpu.h"
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#include "irq.h"
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#include "sched.h"
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#include "thread.h"
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#include "periph/uart.h"
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/**
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* @brief Maximum percentage error in calculated baud before switching to
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* double speed transmission (U2X)
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*
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* Takes whole numbers from 0 to 100, inclusive, with a default of 2.
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*/
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#if defined(UART_BAUD_TOL)
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/* BAUD_TOL is defined here as it is used by the setbaud.h utility */
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#define BAUD_TOL UART_BAUD_TOL
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#else
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#define BAUD_TOL 2
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#endif
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#if defined(STDIO_UART_BAUDRATE)
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/* BAUD and F_CPU are required by setbaud.h to calculated BRR */
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#define BAUD STDIO_UART_BAUDRATE
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#define F_CPU CLOCK_CORECLOCK
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#include <util/setbaud.h>
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#endif
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/**
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* @brief Configured device map
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*/
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static mega_uart_t *dev[] = {
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#ifdef UART_0
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UART_0,
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#endif
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#ifdef UART_1
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UART_1,
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#endif
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#ifdef UART_2
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UART_2,
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#endif
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#ifdef UART_3
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UART_3
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#endif
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};
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/**
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* @brief Allocate memory to store the callback functions.
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*/
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static uart_isr_ctx_t isr_ctx[UART_NUMOF];
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static void _update_brr(uart_t uart, uint16_t brr, bool double_speed)
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{
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#if defined(UCSR0A) || defined(UCSR1A)
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dev[uart]->BRR = brr;
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#elif defined(UCSRA) /* atmega8 */
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/* on atmega8 BRRH is shared with CSRC */
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dev[uart]->CSRC = (brr >> 8);
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dev[uart]->BRRL = (uint8_t)(brr & 0x00ff);
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#endif
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if (double_speed) {
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#if defined(U2X) /* atmega8 */
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dev[uart]->CSRA |= (1 << U2X);
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#elif defined(U2X0)
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dev[uart]->CSRA |= (1 << U2X0);
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#elif defined(U2X1) /* atmega32u4 */
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dev[uart]->CSRA |= (1 << U2X1);
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#endif
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}
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}
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static void _set_brr(uart_t uart, uint32_t baudrate)
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{
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uint16_t brr;
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#if defined(STDIO_UART_BAUDRATE)
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/* UBRR_VALUE and USE_2X are statically computed from <util/setbaud.h> */
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if (baudrate == STDIO_UART_BAUDRATE) {
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_update_brr(uart, UBRR_VALUE, USE_2X);
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return;
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}
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#endif
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/* brr calculation is different from the datasheet to provide better rounding */
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#if defined(UART_DOUBLE_SPEED)
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brr = (CLOCK_CORECLOCK + 4UL * baudrate) / (8UL * baudrate) - 1UL;
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_update_brr(uart, brr, true);
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#else
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brr = (CLOCK_CORECLOCK + 8UL * baudrate) / (16UL * baudrate) - 1UL;
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_update_brr(uart, brr, false);
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#endif
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}
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int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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{
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/* make sure the given device is valid */
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if (uart >= UART_NUMOF) {
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return UART_NODEV;
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}
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uint16_t count = UINT16_MAX;
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while (avr8_is_uart_tx_pending() && count--) {}
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/* register interrupt context */
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isr_ctx[uart].rx_cb = rx_cb;
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isr_ctx[uart].arg = arg;
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/* disable and reset UART */
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#ifdef UCSR1D /* 32u4 */
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dev[uart]->CSRD = 0;
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#endif
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dev[uart]->CSRB = 0;
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dev[uart]->CSRA = 0;
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/* configure UART to 8N1 mode */
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#if defined(UCSZ0) && defined(UCSZ1) /* atmega8 */
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dev[uart]->CSRC = (1 << UCSZ0) | (1 << UCSZ1);
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#elif defined(UCSZ00) && defined(UCSZ01)
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dev[uart]->CSRC = (1 << UCSZ00) | (1 << UCSZ01);
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#elif defined(UCSZ10) && defined(UCSZ11) /* 32u4 */
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dev[uart]->CSRC = (1 << UCSZ10) | (1 << UCSZ11);
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#endif
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/* set clock divider */
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_set_brr(uart, baudrate);
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/* enable RX and TX and their respective interrupt */
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if (rx_cb) {
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#if defined(RXCIE) /* atmega8 */
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dev[uart]->CSRB = ((1 << RXCIE) | (1 << TXCIE) | (1 << RXEN) | (1 << TXEN));
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#elif defined(RXCIE0)
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dev[uart]->CSRB = ((1 << RXCIE0) | (1 << TXCIE0) | (1 << RXEN0) | (1 << TXEN0));
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#elif defined(RXCIE1) /* 32u4 */
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dev[uart]->CSRB = ((1 << RXCIE1) | (1 << TXCIE1) | (1 << RXEN1) | (1 << TXEN1));
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#endif
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}
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else {
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#if defined(TXEN) /* atmega8 */
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dev[uart]->CSRB = ((1 << TXEN) | (1 << TXCIE));
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#elif defined(TXEN0)
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dev[uart]->CSRB = ((1 << TXEN0) | (1 << TXCIE0));
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#elif defined(TXEN1) /* 32u4 */
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dev[uart]->CSRB = ((1 << TXEN1) | (1 << TXCIE1));
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#endif
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}
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return UART_OK;
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}
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void uart_write(uart_t uart, const uint8_t *data, size_t len)
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{
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for (size_t i = 0; i < len; i++) {
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#if defined(UDRE) /* atmega8 */
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while (!(dev[uart]->CSRA & (1 << UDRE))) {};
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#elif defined(UDRE0)
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while (!(dev[uart]->CSRA & (1 << UDRE0))) {}
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#elif defined(UDRE1) /* 32u4 */
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while (!(dev[uart]->CSRA & (1 << UDRE1))) {};
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#endif
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/* start of TX won't finish until no data in UDRn and transmit shift
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register is empty */
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unsigned long state = irq_disable();
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avr8_uart_tx_set_pending(uart);
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irq_restore(state);
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dev[uart]->DR = data[i];
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}
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}
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void uart_poweron(uart_t uart)
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{
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(void)uart;
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/* not implemented (yet) */
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}
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void uart_poweroff(uart_t uart)
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{
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(void)uart;
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/* not implemented (yet) */
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}
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static inline void _rx_isr_handler(int num)
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{
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isr_ctx[num].rx_cb(isr_ctx[num].arg, dev[num]->DR);
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}
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static inline void _tx_isr_handler(int num)
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{
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/* entire frame in the Transmit Shift Register has been shifted out and
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there are no new data currently present in the transmit buffer */
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avr8_uart_tx_clear_pending(num);
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}
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#ifdef UART_0_ISR
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AVR8_ISR(UART_0_ISR, _rx_isr_handler, 0);
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#endif /* UART_0_ISR */
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#ifdef UART_1_ISR
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AVR8_ISR(UART_1_ISR, _rx_isr_handler, 1);
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#endif /* UART_1_ISR */
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#ifdef UART_2_ISR
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AVR8_ISR(UART_2_ISR, _rx_isr_handler, 2);
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#endif /* UART_2_ISR */
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#ifdef UART_3_ISR
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AVR8_ISR(UART_3_ISR, _rx_isr_handler, 3);
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#endif /* UART_3_ISR */
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#ifdef UART_0_ISR_TX
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AVR8_ISR(UART_0_ISR_TX, _tx_isr_handler, 0);
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#endif /* UART_0_ISR_TX */
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#ifdef UART_1_ISR_TX
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AVR8_ISR(UART_1_ISR_TX, _tx_isr_handler, 1);
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#endif /* UART_1_ISR_TX */
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#ifdef UART_2_ISR_TX
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AVR8_ISR(UART_2_ISR_TX, _tx_isr_handler, 2);
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#endif /* UART_2_ISR_TX */
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#ifdef UART_3_ISR_TX
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AVR8_ISR(UART_3_ISR_TX, _tx_isr_handler, 3);
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#endif /* UART_3_ISR_TX */
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