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36e8526046
The API was based on the assumption that GPIO ports are mapped in memory
sanely, so that a `GPIO_PORT(num)` macro would work allow for constant
folding when `num` is known and still be efficient when it is not.
Some MCUs, however, will need a look up tables to efficiently translate
GPIO port numbers to the port's base address. This will prevent the use
of such a `GPIO_PORT(num)` macro in constant initializers.
As a result, we rather provide `GPIO_PORT_0`, `GPIO_PORT_1`, etc. macros
for each GPIO port present (regardless of MCU naming scheme), as well as
`GPIO_PORT_A`, `GPIO_PORT_B`, etc. macros if (and only if) the MCU port
naming scheme uses letters rather than numbers.
These can be defined as macros to the peripheral base address even when
those are randomly mapped into the address space. In addition, a C
function `gpio_port()` replaces the role of the `GPIO_PORT()` and
`gpio_port_num()` the `GPIO_PORT_NUM()` macro. Those functions will
still be implemented as efficient as possible and will allow constant
folding where it was formerly possible. Hence, there is no downside for
MCUs with sane peripheral memory mapping, but it is highly beneficial
for the crazy ones.
There are also two benefits for the non-crazy MCUs:
1. We can now test for valid port numbers with `#ifdef GPIO_PORT_<NUM>`
- This directly benefits the test in `tests/periph/gpio_ll`, which
can now provide a valid GPIO port for each and every board
- Writing to invalid memory mapped I/O addresses was treated as
triggering undefined behavior by the compiler and used as a
optimization opportunity
2. We can now detect at compile time if the naming scheme of the MCU
uses letters or numbers, and produce more user friendly output.
- This is directly applied in the test app
389 lines
10 KiB
C
389 lines
10 KiB
C
/*
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* Copyright (C) 2015 HAW Hamburg
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* 2016 Freie Universität Berlin
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* 2016 INRIA
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* 2023 Hugues Larrive
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_atmega_common
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author René Herthel <rene-herthel@outlook.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Francisco Acosta <francisco.acosta@inria.fr>
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* @author Hugues Larrive <hugues.larrive@pm.me>
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*/
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#ifndef PERIPH_CPU_COMMON_H
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#define PERIPH_CPU_COMMON_H
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#include "cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Length of the CPU_ID in octets
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* @{
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*/
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#define CPUID_LEN (4U)
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/** @} */
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#ifndef DOXYGEN
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/**
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* @brief Overwrite the default gpio_t type definition
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* @{
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*/
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#define HAVE_GPIO_T
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typedef uint8_t gpio_t;
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/** @} */
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#endif
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/**
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* @brief Definition of a fitting UNDEF value
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*/
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#define GPIO_UNDEF (0xff)
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/**
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* @brief Define a CPU specific GPIO pin generator macro
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*/
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#define GPIO_PIN(x, y) ((x << 4) | y)
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/**
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* @brief Base of the GPIO registers as memory address
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*
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* Must be identical to the address of `PINA` provided by avr/io.h
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*/
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#if (defined(OCF1A) && defined(OCF1B) && (OCF1A > OCF1B)) \
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|| (defined(PUD) && (PUD != 4)) || (defined(INT0) && (INT0 == 6))
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/* match with 65 devices against 61 for (PORTB == _SFR_IO8(0x18)) which
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* did not work here anyway */
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#define GPIO_PORT_DESCENDENT
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#endif
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#ifdef GPIO_PORT_DESCENDENT
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#ifdef _AVR_ATTINY1634_H_INCLUDED
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/* the only one that requires particular treatment! */
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#define ATMEGA_GPIO_BASE_A 0x2F
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#else
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/* all other port descendent, including :
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- _AVR_IO8534_ (only have port A but with 0x1B address) ;
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- _AVR_IOAT94K_H_ (only have ports D and E) ;
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- _AVR_IOTN28_H_ (only have ports A and D). */
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#define ATMEGA_GPIO_BASE_A 0x39
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#endif /* _AVR_ATTINY1634_H_INCLUDED */
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#else /* !GPIO_PORT_DESCENDENT */
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#define ATMEGA_GPIO_BASE_A 0x20
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#endif /* GPIO_PORT_DESCENDENT */
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/**
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* @brief Base of the GPIO port G register as memory address
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*
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* Must be identical to the address of `PING` provided by avr/io.h
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*/
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#define ATMEGA_GPIO_BASE_G (ATMEGA_GPIO_BASE_A + ATMEGA_GPIO_SIZE * ('G' - 'A'))
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/**
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* @brief Base of the GPIO registers of the second memory region (port >= H)
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*
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* Must be identical to the address of `PINH` provided by avr/io.h
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*/
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#define ATMEGA_GPIO_BASE_H (0x100)
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/**
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* @brief sizeof(atmega_gpio_port_t), but preprocessor friendly
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*/
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#define ATMEGA_GPIO_SIZE (0x03)
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#if defined(DOXYGEN)
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/**
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* @brief Number of external interrupt vectors
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*/
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#define GPIO_EXT_INT_NUMOF <CPU_SPECIFIC>
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#elif defined(INT7_vect)
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#define GPIO_EXT_INT_NUMOF (8U)
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#elif defined(INT6_vect)
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#define GPIO_EXT_INT_NUMOF (7U)
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#elif defined(INT5_vect)
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#define GPIO_EXT_INT_NUMOF (6U)
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#elif defined(INT4_vect)
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#define GPIO_EXT_INT_NUMOF (5U)
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#elif defined(INT3_vect)
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#define GPIO_EXT_INT_NUMOF (4U)
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#elif defined(INT2_vect)
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#define GPIO_EXT_INT_NUMOF (3U)
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#else
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#define GPIO_EXT_INT_NUMOF (2U)
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#endif
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/**
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* @brief Structure describing the memory layout of the registers of a
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* GPIO port on ATmega MCUs.
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*/
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typedef struct {
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/**
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* @brief Toggle bits in the port register
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* @note The bits in the port register will be also toggled for inputs.
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* This can be both a footgun as well as an efficient way to toggle
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* the pull up resistor on inputs
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*
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* Referred to as "Input Pins Address" in the datasheet.
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*/
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volatile uint8_t pin;
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/**
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* @brief Configure pins as output (1) or input (0) using the Data
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* Direction Register
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*/
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volatile uint8_t ddr;
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/**
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* @brief Read/write the state of GPIO pins using the Port Data Register
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*
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* @note When in input mode (see @ref atmega_gpio_port_t::ddr) writing a
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* 1 will enable the pull up resistor, writing a 0 will put the
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* pin in floating mode.
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*/
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volatile uint8_t port;
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} atmega_gpio_port_t;
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/**
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* @brief Get the GPIO PORT registers of the given GPIO PORT
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* @param[in] port_num Number of the port to get the registers of
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* @return Pointer to the registers controlling the given GPIO PORT
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*/
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static inline atmega_gpio_port_t *atmega_gpio_port(uint8_t port_num)
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{
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static const uintptr_t base_addr = (uintptr_t)ATMEGA_GPIO_BASE_A;
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#ifdef GPIO_PORT_DESCENDENT
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uintptr_t res = base_addr - port_num * sizeof(atmega_gpio_port_t);
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#else
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uintptr_t res = base_addr + port_num * sizeof(atmega_gpio_port_t);
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#endif
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/* GPIO ports up to (including) G are mapped in the I/O address space,
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* port H and higher (if present) are mapped in a different contiguous
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* region afterwards (e.g. 0x100 for ATmega2560). */
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#ifdef PORTH
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if (port_num > 'G'-'A') {
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static const uintptr_t offset = ATMEGA_GPIO_BASE_H - ATMEGA_GPIO_BASE_G;
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res += offset;
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}
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#endif
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return (atmega_gpio_port_t *)res;
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}
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#ifndef DOXYGEN
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/**
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* @brief Override the GPIO flanks
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*
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* This device has an additional mode in which the interrupt is triggered
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* when the pin is low.
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*
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* Enumeration order is important, do not modify.
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* @{
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*/
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#define HAVE_GPIO_FLANK_T
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typedef enum {
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GPIO_LOW, /**< emit interrupt when pin low */
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GPIO_BOTH, /**< emit interrupt on both flanks */
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GPIO_FALLING, /**< emit interrupt on falling flank */
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GPIO_RISING, /**< emit interrupt on rising flank */
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} gpio_flank_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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#ifndef DOXYGEN /* BEGIN: GPIO LL overwrites */
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#define HAVE_GPIO_SLEW_T
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typedef enum {
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GPIO_SLEW_SLOWEST = 0,
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GPIO_SLEW_SLOW = 0,
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GPIO_SLEW_FAST = 0,
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GPIO_SLEW_FASTEST = 0,
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} gpio_slew_t;
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#define HAVE_GPIO_PULL_STRENGTH_T
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typedef enum {
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GPIO_PULL_WEAKEST = 0,
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GPIO_PULL_WEAK = 0,
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GPIO_PULL_STRONG = 0,
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GPIO_PULL_STRONGEST = 0
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} gpio_pull_strength_t;
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#define HAVE_GPIO_DRIVE_STRENGTH_T
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typedef enum {
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GPIO_DRIVE_WEAKEST = 0,
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GPIO_DRIVE_WEAK = 0,
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GPIO_DRIVE_STRONG = 0,
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GPIO_DRIVE_STRONGEST = 0
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} gpio_drive_strength_t;
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#define HAVE_GPIO_IRQ_TRIG_T
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typedef enum {
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GPIO_TRIGGER_LEVEL_LOW = 0x00,
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GPIO_TRIGGER_EDGE_BOTH = 0x01,
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GPIO_TRIGGER_EDGE_FALLING = 0x02,
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GPIO_TRIGGER_EDGE_RISING = 0x03,
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GPIO_TRIGGER_LEVEL_HIGH = 0xff, /**< not supported */
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} gpio_irq_trig_t;
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#define HAVE_GPIO_STATE_T
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typedef enum {
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GPIO_INPUT,
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GPIO_OUTPUT_PUSH_PULL,
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GPIO_OUTPUT_OPEN_DRAIN, /**< not supported */
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GPIO_OUTPUT_OPEN_SOURCE, /**< not supported */
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GPIO_USED_BY_PERIPHERAL, /**< not supported */
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GPIO_DISCONNECT = GPIO_INPUT,
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} gpio_state_t;
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#define HAVE_GPIO_LL_PREPARE_WRITE_ALL_PINS
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#define HAVE_GPIO_LL_PREPARE_WRITE
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#endif /* END: GPIO LL overwrites */
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/**
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* @brief Use some common SPI functions
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* @{
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*/
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#define PERIPH_SPI_NEEDS_INIT_CS
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
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#define PERIPH_SPI_NEEDS_TRANSFER_REG
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#define PERIPH_SPI_NEEDS_TRANSFER_REGS
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/** @} */
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#ifndef DOXYGEN
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/**
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* @brief SPI mode select macro
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*
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* The polarity is determined by bit 3 in the configuration register, the phase
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* by bit 2.
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*/
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#define SPI_MODE_SEL(pol, pha) ((pol << 3) | (pha << 2))
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/**
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* @name Override the SPI mode values
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*
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* As the mode is set in bit 3 and 2 of the configuration register, we put the
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* correct configuration there
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* @{
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*/
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#define HAVE_SPI_MODE_T
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typedef enum {
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SPI_MODE_0 = SPI_MODE_SEL(0, 0), /**< mode 0 */
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SPI_MODE_1 = SPI_MODE_SEL(0, 1), /**< mode 1 */
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SPI_MODE_2 = SPI_MODE_SEL(1, 0), /**< mode 2 */
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SPI_MODE_3 = SPI_MODE_SEL(1, 1) /**< mode 3 */
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} spi_mode_t;
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/** @} */
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/**
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* @brief SPI speed selection macro
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*
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* We encode the speed in bits 2, 1, and 0, where bit0 and bit1 hold the SPCR
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* prescaler bits, while bit2 holds the SPI2X bit.
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*/
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#define SPI_CLK_SEL(s2x, pr1, pr0) ((s2x << 2) | (pr1 << 1) | pr0)
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/**
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* @name Override SPI speed values
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*
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* We assume a master clock speed of 16MHz here.
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* @{
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*/
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#define HAVE_SPI_CLK_T
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typedef enum {
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SPI_CLK_100KHZ = SPI_CLK_SEL(0, 1, 1), /**< 16/128 -> 125KHz */
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SPI_CLK_400KHZ = SPI_CLK_SEL(1, 1, 0), /**< 16/32 -> 500KHz */
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SPI_CLK_1MHZ = SPI_CLK_SEL(0, 0, 1), /**< 16/16 -> 1MHz */
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SPI_CLK_5MHZ = SPI_CLK_SEL(0, 0, 0), /**< 16/4 -> 4MHz */
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SPI_CLK_10MHZ = SPI_CLK_SEL(1, 0, 0) /**< 16/2 -> 8MHz */
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} spi_clk_t;
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/** @} */
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#endif /* ifndef DOXYGEN */
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/**
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* @name Bitmasks indicating which are the possible dividers for a timer
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* @{
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*/
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typedef enum {
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TIMER_DIV1_8_64_128_1024 = 0x549, /**< 1/{1,8,64,128,1024} */
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TIMER_DIV1_8_32_64_128_256_1024 = 0x5E9, /**< 1/{1,8,32,64,128,256,1024} */
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} timer_div_t;
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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typedef struct {
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mini_timer_t *dev; /**< Timer used */
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gpio_t pin_ch[2]; /**< Output Pins */
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timer_div_t div; /**< Timer divider mask */
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} pwm_conf_t;
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/** @} */
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/**
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* @brief A low-level timer_set() implementation is provided
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*/
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#define PERIPH_TIMER_PROVIDES_SET
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/**
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* @brief EEPROM clear byte
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*/
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#define EEPROM_CLEAR_BYTE (0xff)
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/**
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* @name WDT upper and lower bound times in ms
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* @{
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*/
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#define NWDT_TIME_LOWER_LIMIT (1)
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#define NWDT_TIME_UPPER_LIMIT (8192U)
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/** @} */
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/**
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* @brief WDT can be stopped on AVR
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*/
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#define WDT_HAS_STOP (1)
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/**
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* @name RTT configuration
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* @{
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*/
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#if defined(SCCR0) && !defined(RTT_BACKEND_SC)
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#define RTT_BACKEND_SC (1)
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#endif
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#if RTT_BACKEND_SC
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/* For MCU with MAC symbol counter */
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#ifndef RTT_MAX_VALUE
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#define RTT_MAX_VALUE (0xFFFFFFFFUL) /* 32-bit timer */
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#endif
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#ifndef RTT_FREQUENCY
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#define RTT_FREQUENCY (62500UL) /* in Hz. */
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#endif
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#else
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/* For MCU without MAC symbol counter */
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#ifndef RTT_MAX_VALUE
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#define RTT_MAX_VALUE (0x00FFFFFF) /* 24-bit timer */
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#endif
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/* possible values: 32, 128, 256, 512, 1024, 4096, 32768 */
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#ifndef RTT_FREQUENCY
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#define RTT_FREQUENCY (1024U) /* in Hz. */
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#endif
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_COMMON_H */
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/** @} */
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