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36e8526046
The API was based on the assumption that GPIO ports are mapped in memory
sanely, so that a `GPIO_PORT(num)` macro would work allow for constant
folding when `num` is known and still be efficient when it is not.
Some MCUs, however, will need a look up tables to efficiently translate
GPIO port numbers to the port's base address. This will prevent the use
of such a `GPIO_PORT(num)` macro in constant initializers.
As a result, we rather provide `GPIO_PORT_0`, `GPIO_PORT_1`, etc. macros
for each GPIO port present (regardless of MCU naming scheme), as well as
`GPIO_PORT_A`, `GPIO_PORT_B`, etc. macros if (and only if) the MCU port
naming scheme uses letters rather than numbers.
These can be defined as macros to the peripheral base address even when
those are randomly mapped into the address space. In addition, a C
function `gpio_port()` replaces the role of the `GPIO_PORT()` and
`gpio_port_num()` the `GPIO_PORT_NUM()` macro. Those functions will
still be implemented as efficient as possible and will allow constant
folding where it was formerly possible. Hence, there is no downside for
MCUs with sane peripheral memory mapping, but it is highly beneficial
for the crazy ones.
There are also two benefits for the non-crazy MCUs:
1. We can now test for valid port numbers with `#ifdef GPIO_PORT_<NUM>`
- This directly benefits the test in `tests/periph/gpio_ll`, which
can now provide a valid GPIO port for each and every board
- Writing to invalid memory mapped I/O addresses was treated as
triggering undefined behavior by the compiler and used as a
optimization opportunity
2. We can now detect at compile time if the naming scheme of the MCU
uses letters or numbers, and produce more user friendly output.
- This is directly applied in the test app
377 lines
8.7 KiB
C
377 lines
8.7 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_atmega_common
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* @ingroup drivers_periph_gpio_ll
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* @{
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*
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* @file
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* @brief CPU specific part of the Peripheral GPIO Low-Level API
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*
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* @note This GPIO driver implementation supports only one pin to be
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* defined as external interrupt.
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef GPIO_LL_ARCH_H
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#define GPIO_LL_ARCH_H
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#include <assert.h>
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#include "cpu.h"
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#include "irq.h"
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#include "kernel_defines.h"
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef DOXYGEN /* hide implementation specific details from Doxygen */
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/* AVR generally requires two CPU cycles for loads from and stores to memory.
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* However, there are special single cycle instructions, which however require
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* the target address to be given as an 5 bit immediate. So only a 64 byte sized
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* part of the data address space can be accessed this way, which is called
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* the I/O memory (as (almost) only memory mapped I/O is mapped there).
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*
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* GPIO ports up to G are part of the I/O mapped area, but starting from port H
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* the GPIO registers are only accessible via regular load and store operations
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* and mapped slightly different in the data address space. For some reason,
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* there is a gap between the GPIO memory regions for port A to G and H and
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* above that results in special handling for GPIO ports H and above.
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*
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* Note that this implementation always uses the data address way to access GPIO
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* registers and never the single cycle instructions. However, GCC converts the
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* instructions into semantically equivalent single CPU cycle instructions
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* whenever the target address is known at compile time (so can be expressed as
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* immediate) and also mapped into the I/O address space. We rely on this
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* optimization to claim single cycle GPIO accesses for GPIO ports below H,
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* whenever the port number is known at compile time.
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*/
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#define GPIO_PORT_NUMBERING_ALPHABETIC 1
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#ifdef PINA
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/* We sadly cannot use PINA, as PINA is technically (in terms of C spec lingo)
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* not constant and would trigger:
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* initializer element is not constant
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* Hence, the defines are a bit more involved to yield proper constants
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* suitable for initializers.
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*/
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# define GPIO_PORT_0 (ATMEGA_GPIO_BASE_A)
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#endif
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#ifdef PINB
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# define GPIO_PORT_1 (ATMEGA_GPIO_BASE_A + 1 * ATMEGA_GPIO_SIZE)
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#endif
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#ifdef PINC
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# define GPIO_PORT_2 (ATMEGA_GPIO_BASE_A + 2 * ATMEGA_GPIO_SIZE)
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#endif
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#ifdef PIND
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# define GPIO_PORT_3 (ATMEGA_GPIO_BASE_A + 3 * ATMEGA_GPIO_SIZE)
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#endif
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#ifdef PINE
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# define GPIO_PORT_4 (ATMEGA_GPIO_BASE_A + 4 * ATMEGA_GPIO_SIZE)
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#endif
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#ifdef PINF
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# define GPIO_PORT_5 (ATMEGA_GPIO_BASE_A + 5 * ATMEGA_GPIO_SIZE)
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#endif
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#ifdef PING
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# define GPIO_PORT_6 (ATMEGA_GPIO_BASE_A + 6 * ATMEGA_GPIO_SIZE)
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#endif
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/* There is a larger gap between PING and PINH to allow other peripherals to
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* also be mapped into the fast I/O memory area. */
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#ifdef PINH
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# define GPIO_PORT_7 (ATMEGA_GPIO_BASE_H)
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#endif
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#ifdef PINI
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# define GPIO_PORT_8 (ATMEGA_GPIO_BASE_H + 1 * ATMEGA_GPIO_SIZE)
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#endif
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#ifdef PINJ
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# define GPIO_PORT_9 (ATMEGA_GPIO_BASE_H + 2 * ATMEGA_GPIO_SIZE)
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#endif
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#ifdef PINK
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# define GPIO_PORT_10 (ATMEGA_GPIO_BASE_H + 3 * ATMEGA_GPIO_SIZE)
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#endif
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#ifdef PINL
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# define GPIO_PORT_11 (ATMEGA_GPIO_BASE_H + 4 * ATMEGA_GPIO_SIZE)
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#endif
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static inline gpio_port_t gpio_port(uword_t num)
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{
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#ifdef PINH
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if (num >= PORT_H) {
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return ATMEGA_GPIO_BASE_H + ((num - PORT_H) * ATMEGA_GPIO_SIZE);
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}
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#endif
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return ATMEGA_GPIO_BASE_A + (num * ATMEGA_GPIO_SIZE);
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}
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static inline uword_t gpio_port_num(gpio_port_t port)
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{
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#ifdef PINH
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if ((port) >= ATMEGA_GPIO_BASE_H) {
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return (port - ATMEGA_GPIO_BASE_H) / ATMEGA_GPIO_SIZE + PORT_H;
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}
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#endif
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return (port - ATMEGA_GPIO_BASE_A) / ATMEGA_GPIO_SIZE;
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}
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static inline uword_t gpio_ll_read(gpio_port_t port)
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{
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atmega_gpio_port_t *p = (void *)port;
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return p->pin;
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}
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static inline uword_t gpio_ll_read_output(gpio_port_t port)
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{
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atmega_gpio_port_t *p = (void *)port;
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return p->port;
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}
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/**
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* @brief Check if a set/clear operation with the on the given port with the
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* given mask can be done in a single-cycle bit-set / bit-clear
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* instruction.
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*
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* @param port GPIO port to set/clear bits on
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* @param mask Bitmask specifying the bits to set/clear
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*
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* The compiler can optimize a clear/set operation if all of the following is
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* true:
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*
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* 1. The GPIO port number is known at compile time, so that it can be used as
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* immediate
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* 2. The GPIO port is alphabetically smaller than H, otherwise its registers
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* are not within the I/O space (and cannot fit the 5 bit immediate field)
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* 3. The bitmask is known at compile time
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* 4. Exactly one bit is set in the bitmask
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*/
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static inline bool _can_bitwise_access(gpio_port_t port, uword_t mask)
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{
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if (IS_CT_CONSTANT(port)
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#ifdef ATMEGA_GPIO_BASE_H
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&& IS_CT_CONSTANT(port < ATMEGA_GPIO_BASE_H)
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&& (port < ATMEGA_GPIO_BASE_H)
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#endif
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&& IS_CT_CONSTANT(mask)
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&& IS_CT_CONSTANT(__builtin_popcount(mask) == 1)) {
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return __builtin_popcount(mask) == 1;
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}
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return 0;
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}
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static inline void gpio_ll_set(gpio_port_t port, uword_t mask)
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{
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atmega_gpio_port_t *p = (void *)port;
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if (_can_bitwise_access(port, mask)) {
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p->port |= mask;
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}
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else {
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unsigned state = irq_disable();
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p->port |= mask;
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irq_restore(state);
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}
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}
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static inline void gpio_ll_clear(gpio_port_t port, uword_t mask)
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{
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atmega_gpio_port_t *p = (void *)port;
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if (_can_bitwise_access(port, mask)) {
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p->port &= ~mask;
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}
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else {
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unsigned state = irq_disable();
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p->port &= ~mask;
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irq_restore(state);
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}
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}
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static inline void gpio_ll_toggle(gpio_port_t port, uword_t mask)
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{
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atmega_gpio_port_t *p = (void *)port;
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/* this is equivalent to `p->port ^= mask`, but faster and inherently
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* atomically */
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p->pin = mask;
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}
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static inline void gpio_ll_write(gpio_port_t port, uword_t value)
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{
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atmega_gpio_port_t *p = (void *)port;
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p->port = value;
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}
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static inline gpio_port_t gpio_get_port(gpio_t pin)
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{
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return gpio_port(pin >> 4);
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}
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static inline uint8_t gpio_get_pin_num(gpio_t pin)
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{
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return pin & 0x0f;
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}
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static inline uword_t gpio_ll_prepare_write_all_outputs(gpio_port_t port,
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uword_t value)
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{
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atmega_gpio_port_t *p = (void *)port;
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uword_t result = (gpio_ll_read_output(port) & (~p->ddr)) | value;
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return result;
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}
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static inline uword_t gpio_ll_prepare_write(gpio_port_t port, uword_t mask,
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uword_t value)
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{
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atmega_gpio_port_t *p = (void *)port;
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uword_t result = gpio_ll_read_output(port);
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result &= (~p->ddr) | (~mask);
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result |= value;
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return result;
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}
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static inline void gpio_ll_switch_dir_output(gpio_port_t port, uword_t outputs)
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{
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unsigned irq_state = irq_disable();
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atmega_gpio_port_t *p = (void *)port;
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p->ddr |= outputs;
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irq_restore(irq_state);
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}
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static inline void gpio_ll_switch_dir_input(gpio_port_t port, uword_t inputs)
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{
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unsigned irq_state = irq_disable();
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atmega_gpio_port_t *p = (void *)port;
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p->ddr &= ~(inputs);
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irq_restore(irq_state);
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}
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static inline gpio_port_t gpio_port_pack_addr(void *addr)
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{
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return (gpio_port_t)addr;
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}
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static inline void * gpio_port_unpack_addr(gpio_port_t port)
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{
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if (port < RAMSTART) {
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return NULL;
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}
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return (void *)port;
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}
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static inline bool is_gpio_port_num_valid(uint_fast8_t num)
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{
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switch (num) {
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default:
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return false;
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#ifdef DDRA
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case 0:
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#endif
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#ifdef DDRB
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case 1:
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#endif
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#ifdef DDRC
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case 2:
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#endif
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#ifdef DDRD
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case 3:
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#endif
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#ifdef DDRE
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case 4:
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#endif
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#ifdef DDRF
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case 5:
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#endif
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#ifdef DDRG
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case 6:
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#endif
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#ifdef DDRH
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case 7:
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#endif
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#ifdef DDRI
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case 8:
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#endif
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#ifdef DDRJ
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case 9:
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#endif
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#ifdef DDRK
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case 10:
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#endif
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#ifdef DDRL
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case 11:
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#endif
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#ifdef DDRM
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case 12:
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#endif
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#ifdef DDRN
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case 13:
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#endif
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#ifdef DDRO
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case 14:
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#endif
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#ifdef DDRP
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case 15:
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#endif
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#ifdef DDRQ
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case 16:
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#endif
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#ifdef DDRR
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case 17:
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#endif
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#ifdef DDRS
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case 18:
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#endif
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#ifdef DDRT
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case 19:
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#endif
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#ifdef DDRU
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case 20:
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#endif
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#ifdef DDRV
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case 21:
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#endif
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#ifdef DDRW
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case 22:
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#endif
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#ifdef DDRX
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case 23:
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#endif
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#ifdef DDRY
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case 24:
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#endif
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#ifdef DDRZ
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case 25:
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#endif
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return true;
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}
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}
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#endif /* DOXYGEN */
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#ifdef __cplusplus
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}
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#endif
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#endif /* GPIO_LL_ARCH_H */
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/** @} */
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