mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
d2a3ff3d83
- renamed:
- `bluepill` --> `bluepill-stm32f103c8`
- `bluepill-128kib` --> `bluepill-stm32f103cb`
- `blackpill` --> `blackpill-stm32f103c8`
- `blackpill-128kib` --> `blackpill-stm32f103cb`
- doc:
- added link to corresponding hardware page on the STM32-base
project
- added picture
375 lines
10 KiB
C
375 lines
10 KiB
C
/*
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* Copyright (C) 2015 TriaGnoSys GmbH
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* 2017 Alexander Kurth, Sören Tempel, Tristan Bruns
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_blxxxpill
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the bluepill/blackpill boards
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*
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* @author Víctor Ariño <victor.arino@triagnosys.com>
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* @author Sören Tempel <tempel@uni-bremen.de>
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* @author Tristan Bruns <tbruns@uni-bremen.de>
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* @author Alexander Kurth <kurth1@uni-bremen.de>
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*
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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/* blxxxpill boards provide an LSE */
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#ifndef CONFIG_BOARD_HAS_LSE
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#define CONFIG_BOARD_HAS_LSE 1
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#endif
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/* blxxxpill boards provide an HSE */
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#ifndef CONFIG_BOARD_HAS_HSE
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#define CONFIG_BOARD_HAS_HSE 1
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#endif
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#include "periph_cpu.h"
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#include "clk_conf.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Real time counter configuration
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* @{
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*/
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#ifndef RTT_FREQUENCY
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#define RTT_FREQUENCY (16384) /* in Hz */
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#endif
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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static const adc_conf_t adc_config[] = {
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{ .pin = GPIO_PIN(PORT_A, 0), .dev = 0, .chan = 0 },
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{ .pin = GPIO_PIN(PORT_A, 1), .dev = 0, .chan = 1 },
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{ .pin = GPIO_PIN(PORT_A, 4), .dev = 0, .chan = 4 },
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{ .pin = GPIO_PIN(PORT_A, 5), .dev = 0, .chan = 5 },
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{ .pin = GPIO_PIN(PORT_A, 6), .dev = 0, .chan = 6 },
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{ .pin = GPIO_PIN(PORT_A, 7), .dev = 0, .chan = 7 },
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/* ADC Temperature channel */
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{ .pin = GPIO_UNDEF, .dev = 0, .chan = 16 },
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/* ADC VREF channel */
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{ .pin = GPIO_UNDEF, .dev = 0, .chan = 17 },
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/* The blackpill has a few pins less. PB0 and PB1 are among the GPIOs not
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* exposed due to the lower pincount.
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*
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* Also, this conflicts with PWM. We prefer PWM over ADC here to provide
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* 6 external ADC inputs, and 4 PWM outputs (instead of 8 ADC inputs and
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* 2 PWM outputs). */
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#if !defined(BOARD_BLACKPILL_STM32F103C8) \
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&& !defined(BOARD_BLACKPILL_STM32F103CB) \
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&& !defined(MODULE_PERIPH_PWM)
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{ .pin = GPIO_PIN(PORT_B, 0), .dev = 0, .chan = 8 },
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{ .pin = GPIO_PIN(PORT_B, 1), .dev = 0, .chan = 9 },
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#endif
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};
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#define ADC_NUMOF ARRAY_SIZE(adc_config)
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/** @} */
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/**
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* @name DMA streams configuration
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* @{
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*/
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static const dma_conf_t dma_config[] = {
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{ .stream = 1 }, /* DMA1 Channel 2 - SPI1_RX / USART3_TX */
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{ .stream = 2 }, /* DMA1 Channel 3 - SPI1_TX */
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{ .stream = 3 }, /* DMA1 Channel 4 - SPI2_RX / USART1_TX */
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{ .stream = 4 }, /* DMA1 Channel 5 - SPI2_TX */
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{ .stream = 6 }, /* DMA1 Channel 7 - USART2_TX */
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};
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#define DMA_0_ISR isr_dma1_channel2
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#define DMA_1_ISR isr_dma1_channel3
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#define DMA_2_ISR isr_dma1_channel4
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#define DMA_3_ISR isr_dma1_channel5
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#define DMA_4_ISR isr_dma1_channel7
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#define DMA_NUMOF ARRAY_SIZE(dma_config)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM2,
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.max = 0x0000ffff,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.bus = APB1,
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.irqn = TIM2_IRQn
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},
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{
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.dev = TIM3,
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.max = 0x0000ffff,
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.rcc_mask = RCC_APB1ENR_TIM3EN,
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.bus = APB1,
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.irqn = TIM3_IRQn
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},
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{
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.dev = TIM4,
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.max = 0x0000ffff,
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.rcc_mask = RCC_APB1ENR_TIM4EN,
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.bus = APB1,
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.irqn = TIM4_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim2
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#define TIMER_1_ISR isr_tim3
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#define TIMER_2_ISR isr_tim4
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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/** @} */
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/**
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* @name QDEC configuration
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* @{
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*/
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static const qdec_conf_t qdec_config[] = {
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{
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.dev = TIM4,
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.max = 0x0000ffff,
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.rcc_mask = RCC_APB1ENR_TIM4EN,
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.chan = { { .pin = GPIO_PIN(PORT_B, 6), .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_B, 7), .cc_chan = 1 } },
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.bus = APB1,
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.irqn = TIM4_IRQn,
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},
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/* this conflicts with PWM */
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#ifndef MODULE_PERIPH_PWM
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{
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.dev = TIM3,
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.max = 0x0000ffff,
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.rcc_mask = RCC_APB1ENR_TIM3EN,
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.chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_B, 5), .cc_chan = 1 } },
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/* by default TIM3 is routed to PA6 (cc_chan 0) and PA7 (cc_chan 1) */
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.remap = AFIO_MAPR_TIM3_REMAP_1,
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.bus = APB1,
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.irqn = TIM3_IRQn,
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},
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#endif
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/* this conflicts with UART_DEV(0) */
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#ifndef MODULE_PERIPH_UART
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{
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.dev = TIM1,
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.max = 0x0000ffff,
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.rcc_mask = RCC_APB2ENR_TIM1EN,
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.chan = { { .pin = GPIO_PIN(PORT_A, 8), .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_A, 9), .cc_chan = 1 } },
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.bus = APB2,
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.irqn = TIM1_UP_IRQn
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},
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#endif
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};
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#define QDEC_NUMOF ARRAY_SIZE(qdec_config)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_A, 10),
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.tx_pin = GPIO_PIN(PORT_A, 9),
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.bus = APB2,
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.irqn = USART1_IRQn,
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#ifdef MODULE_PERIPH_DMA
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.dma = 2,
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.dma_chan = DMA_CHAN_CONFIG_UNSUPPORTED
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#endif
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},
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 3),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.bus = APB1,
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.irqn = USART2_IRQn,
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#ifdef MODULE_PERIPH_DMA
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.dma = 4,
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.dma_chan = DMA_CHAN_CONFIG_UNSUPPORTED
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#endif
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},
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{
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.dev = USART3,
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.rcc_mask = RCC_APB1ENR_USART3EN,
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.rx_pin = GPIO_PIN(PORT_B, 11),
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.tx_pin = GPIO_PIN(PORT_B, 10),
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.bus = APB1,
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.irqn = USART3_IRQn,
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#ifdef MODULE_PERIPH_DMA
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.dma = 0,
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.dma_chan = DMA_CHAN_CONFIG_UNSUPPORTED
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#endif
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}
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};
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#define UART_0_ISR (isr_usart1)
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#define UART_1_ISR (isr_usart2)
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#define UART_2_ISR (isr_usart3)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name I2C configuration
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* @note This board may require external pullup resistors for i2c operation.
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.dev = I2C1,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_B, 8),
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.sda_pin = GPIO_PIN(PORT_B, 9),
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.bus = APB1,
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.rcc_mask = RCC_APB1ENR_I2C1EN,
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.clk = CLOCK_APB1,
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.irqn = I2C1_EV_IRQn
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},
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{
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.dev = I2C2,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_B, 10),
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.sda_pin = GPIO_PIN(PORT_B, 11),
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.bus = APB1,
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.rcc_mask = RCC_APB1ENR_I2C2EN,
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.clk = CLOCK_APB1,
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.irqn = I2C2_EV_IRQn
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}
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};
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#define I2C_0_ISR isr_i2c1_ev
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#define I2C_1_ISR isr_i2c2_ev
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#define I2C_NUMOF ARRAY_SIZE(i2c_config)
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.dev = TIM3,
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.rcc_mask = RCC_APB1ENR_TIM3EN,
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/* by default TIM3 is routed to PA6 (cc_chan 0) and PA7 (cc_chan 1) */
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.remap = AFIO_MAPR_TIM3_REMAP_1,
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.chan = {
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{ .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_B, 5), .cc_chan = 1 },
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#if !defined(BOARD_BLACKPILL_STM32F103C8) \
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&& !defined(BOARD_BLACKPILL_STM32F103CB)
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/* The blackpill has a few pins less. PB0 and PB1 are
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* among the GPIOs not exposed due to the lower
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* pincount */
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{ .pin = GPIO_PIN(PORT_B, 0), .cc_chan = 2 },
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{ .pin = GPIO_PIN(PORT_B, 1), .cc_chan = 3 },
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#endif
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},
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.af = GPIO_AF_OUT_PP,
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.bus = APB1,
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},
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};
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#define PWM_NUMOF ARRAY_SIZE(pwm_config)
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI2,
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.mosi_pin = GPIO_PIN(PORT_B, 15),
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.miso_pin = GPIO_PIN(PORT_B, 14),
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.sclk_pin = GPIO_PIN(PORT_B, 13),
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.cs_pin = GPIO_PIN(PORT_B, 12),
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.rccmask = RCC_APB1ENR_SPI2EN,
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.apbbus = APB1,
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#ifdef MODULE_PERIPH_DMA
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.tx_dma = 3,
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.tx_dma_chan = DMA_CHAN_CONFIG_UNSUPPORTED,
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.rx_dma = 2,
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.rx_dma_chan = DMA_CHAN_CONFIG_UNSUPPORTED
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#endif
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},
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#ifndef MODULE_PERIPH_ADC
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_PIN(PORT_A, 4),
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2,
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#ifdef MODULE_PERIPH_DMA
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.tx_dma = 1,
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.tx_dma_chan = DMA_CHAN_CONFIG_UNSUPPORTED,
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.rx_dma = 0,
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.rx_dma_chan = DMA_CHAN_CONFIG_UNSUPPORTED
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#endif
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},
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#endif
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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/**
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* @brief USB device FS configuration
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*/
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static const stm32_usbdev_fs_config_t stm32_usbdev_fs_config[] = {
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{
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.base_addr = (uintptr_t)USB,
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.rcc_mask = RCC_APB1ENR_USBEN,
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.irqn = USB_LP_CAN1_RX0_IRQn,
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.apb = APB1,
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.dm = GPIO_PIN(PORT_A, 11),
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.dp = GPIO_PIN(PORT_A, 12),
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.af = GPIO_AF_UNDEF,
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.disconn = GPIO_UNDEF,
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},
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};
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/**
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* @brief Interrupt function name mapping
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*/
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#define USBDEV_ISR isr_usb_lp_can1_rx0
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/**
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* @brief Number of available USB device FS peripherals
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*/
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#define USBDEV_NUMOF ARRAY_SIZE(stm32_usbdev_fs_config)
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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