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RIOT/cpu/samd5x/include/periph_cpu.h
Benjamin Valentin fd9a247200 cpu/sam0_common: use generic exti_config
Creating an `exti_config` array for a new MCU manually is tedious and error prone.
Luckiely all information is already availiable in the vendor files.

Credit for this discovery & method goes to @Sizurka

The file was generated with

```C

int main(void) {
        puts("static const int8_t exti_config[PORT_GROUPS][32] = {");

        for (unsigned port = 1; port < 5; ++port) {
                printf("#if PORT_GROUPS >= %d\n{\n", port);
                for (unsigned pin = 0; pin < 32; ++pin) {
                        printf("#ifdef PIN_P%c%02uA_EIC_EXTINT_NUM\n", '@' + port, pin);
                        printf("    PIN_P%c%02uA_EIC_EXTINT_NUM,\n", '@' + port, pin);
                        printf("#else\n    -1,\n#endif\n");
                }
                printf("},\n#endif\n\n");
        }

        puts("};");

        return 0;
}
```

No changes in generated code are expected, but this makes adding new members
of the sam0 CPU families much easier.
2020-02-20 11:23:51 +01:00

71 lines
1.5 KiB
C

/*
* Copyright (C) 2019 ML!PA Consulting GmbH
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup cpu_samd5x
* @brief CPU specific definitions for internal peripheral handling
* @{
*
* @file
* @brief CPU specific definitions for internal peripheral handling
*
* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
*/
#ifndef PERIPH_CPU_H
#define PERIPH_CPU_H
#include <limits.h>
#include "periph_cpu_common.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief DFLL runs at at fixed frequency of 48 MHz
*/
#define SAM0_DFLL_FREQ_HZ (48000000U)
/**
* @brief DPLL must run with at least 96 MHz
*/
#define SAM0_DPLL_FREQ_MIN_HZ (96000000U)
/**
* @brief DPLL frequency must not exceed 200 MHz
*/
#define SAM0_DPLL_FREQ_MAX_HZ (200000000U)
/**
* @name SAMD5x GCLK definitions
* @{
*/
enum {
SAM0_GCLK_MAIN = 0, /**< 120 MHz main clock */
SAM0_GCLK_32KHZ, /**< 32 kHz clock */
SAM0_GCLK_8MHZ, /**< 8 MHz clock for xTimer */
SAM0_GCLK_48MHZ, /**< 48 MHz DFLL clock */
};
/** @} */
/**
* @brief Override SPI hardware chip select macro
*
* As of now, we do not support HW CS, so we always set it to a fixed value
*/
#define SPI_HWCS(x) (UINT_MAX - 1)
#ifdef __cplusplus
}
#endif
#endif /* PERIPH_CPU_H */
/** @} */