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35a1b60068
core_panic() doesn't expect the message to be in program memory, but in data memory. Bad things will happen on AVR when the address is interpreted as being in data address space, but the allocation is done in program address space.
124 lines
3.5 KiB
C
124 lines
3.5 KiB
C
/*
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* Copyright (C) 2021 Gerson Fernando Budke
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_atxmega
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* @{
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*
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* @file
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* @brief Implementation of the CPU initialization
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*
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* @author Gerson Fernando Budke <nandojve@gmail.com>
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* @}
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*/
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#include "cpu.h"
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#include "cpu_clock.h"
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#include "cpu_pm.h"
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#include "panic.h"
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#define ENABLE_DEBUG 0
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#include "debug.h"
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#ifndef CPU_ATXMEGA_CLK_SCALE_INIT
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#define CPU_ATXMEGA_CLK_SCALE_INIT CPU_ATXMEGA_CLK_SCALE_DIV1
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#endif
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#ifndef CPU_ATXMEGA_BUS_SCALE_INIT
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#define CPU_ATXMEGA_BUS_SCALE_INIT CPU_ATXMEGA_BUS_SCALE_DIV1_1
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#endif
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extern uint8_t mcusr_mirror;
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void avr8_reset_cause(void)
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{
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if (mcusr_mirror & (1 << RST_PORF_bp)) {
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DEBUG("Power-on reset.\n");
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}
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if (mcusr_mirror & (1 << RST_EXTRF_bp)) {
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DEBUG("External reset!\n");
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}
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if (mcusr_mirror & (1 << RST_BORF_bp)) {
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DEBUG("Brown-out reset!\n");
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}
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if (mcusr_mirror & (1 << RST_WDRF_bp)) {
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DEBUG("Watchdog reset!\n");
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}
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if (mcusr_mirror & (1 << RST_PDIRF_bp)) {
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DEBUG("Programming and Debug Interface reset!\n");
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}
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if (mcusr_mirror & (1 << RST_SRF_bp)) {
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DEBUG("Software reset!\n");
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}
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if (mcusr_mirror & (1 << RST_SDRF_bp)) {
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DEBUG("Spike Detection reset!\n");
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}
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}
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void __attribute__((weak)) avr8_clk_init(void)
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{
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pm_periph_power_off();
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/* XMEGA A3U [DATASHEET] p.23 After reset, the device starts up running
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* from the 2MHz internal oscillator. The other clock sources, DFLLs
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* and PLL, are turned off by default.
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*
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* Configure clock to 32MHz with calibration
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* application note AVR1003
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*
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* From errata http://www.avrfreaks.net/forum/xmega-dfll-does-it-work
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* In order to use the automatic runtime calibration for the 2 MHz or
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* the 32 MHz internal oscillators, the DFLL for both oscillators and
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* both oscillators has to be enabled for one to work.
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*/
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OSC.PLLCTRL = 0;
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/* Enable the internal PLL & 32MHz & 32KHz oscillators */
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OSC.CTRL |= OSC_PLLEN_bm | OSC_RC32MEN_bm | OSC_RC32KEN_bm;
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/* Wait for 32Khz and 32MHz oscillator to stabilize */
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while ((OSC.STATUS & (OSC_RC32KRDY_bm | OSC_RC32MRDY_bm))
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!= (OSC_RC32KRDY_bm | OSC_RC32MRDY_bm)) {}
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/* Enable DFLL - defaults to calibrate against internal 32Khz clock */
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DFLLRC2M.CTRL = DFLL_ENABLE_bm;
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/* Enable DFLL - defaults to calibrate against internal 32Khz clock */
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DFLLRC32M.CTRL = DFLL_ENABLE_bm;
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/* Some ATxmega need sync clocks after enable DFLL. Otherwise clock may
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* stay at 2MHz source when try enable.
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*/
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while ((OSC.STATUS & OSC_RC32MRDY_bm) != OSC_RC32MRDY_bm) {}
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atxmega_set_prescaler(CPU_ATXMEGA_CLK_SCALE_INIT,
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CPU_ATXMEGA_BUS_SCALE_INIT);
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/* Disable CCP for Protected IO register and set new value*/
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/* Switch to 32MHz clock */
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_PROTECTED_WRITE(CLK.CTRL, CLK_SCLKSEL_RC32M_gc);
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}
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/* This is a vector which is aliased to __vector_default,
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* the vector executed when an ISR fires with no accompanying
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* ISR handler. This may be used along with the ISR() macro to
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* create a catch-all for undefined but used ISRs for debugging
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* purposes.
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*/
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ISR(BADISR_vect)
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{
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avr8_reset_cause();
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#ifdef LED_PANIC
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/* Use LED light to signal ERROR. */
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LED_PANIC;
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#endif
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core_panic(PANIC_GENERAL_ERROR, "BADISR");
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}
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