mirror of
https://github.com/RIOT-OS/RIOT.git
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381 lines
11 KiB
C
381 lines
11 KiB
C
/*
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* Copyright (C) 2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_sam0_common
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* @brief Common CPU specific definitions for all SAMx21 based CPUs
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* @{
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*
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* @file
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* @brief Common CPU specific definitions for all SAMx21 based CPUs
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Dylan Laduranty <dylan.laduranty@mesotic.com>
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*/
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#ifndef PERIPH_CPU_COMMON_H
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#define PERIPH_CPU_COMMON_H
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#include "cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Length of the CPU_ID in octets
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*/
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#define CPUID_LEN (16U)
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/**
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* @brief Use shared SPI functions
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* @{
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*/
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#define PERIPH_SPI_NEEDS_INIT_CS
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
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#define PERIPH_SPI_NEEDS_TRANSFER_REG
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#define PERIPH_SPI_NEEDS_TRANSFER_REGS
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/** @} */
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/**
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* @name Use shared I2C functions
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* @{
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*/
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#define PERIPH_I2C_NEED_READ_REG
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#define PERIPH_I2C_NEED_READ_REGS
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#define PERIPH_I2C_NEED_WRITE_REG
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#define PERIPH_I2C_NEED_WRITE_REGS
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/** @} */
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/**
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* @brief Override GPIO type
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* @{
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*/
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#define HAVE_GPIO_T
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typedef uint32_t gpio_t;
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/** @} */
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/**
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* @brief Definition of a fitting UNDEF value
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*/
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#define GPIO_UNDEF (0xffffffff)
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/**
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* @brief Macro for accessing GPIO pins
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* @{
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*/
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#define GPIO_PIN(x, y) (((gpio_t)(&PORT->Group[x])) | y)
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/**
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* @brief Available ports on the SAMD21 & SAML21
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*/
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enum {
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PA = 0, /**< port A */
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PB = 1, /**< port B */
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PC = 2, /**< port C */
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};
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/**
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* @brief Generate GPIO mode bitfields
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*
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* We use 3 bit to determine the pin functions:
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* - bit 0: PD(0) or PU(1)
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* - bit 1: input enable
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* - bit 2: pull enable
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*/
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#define GPIO_MODE(pr, ie, pe) (pr | (ie << 1) | (pe << 2))
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/**
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* @name Power mode configuration
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* @{
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*/
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#define PM_NUM_MODES (3)
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/** @} */
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#ifndef DOXYGEN
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/**
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* @brief Override GPIO modes
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*/
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#define HAVE_GPIO_MODE_T
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typedef enum {
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GPIO_IN = GPIO_MODE(0, 1, 0), /**< IN */
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GPIO_IN_PD = GPIO_MODE(0, 1, 1), /**< IN with pull-down */
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GPIO_IN_PU = GPIO_MODE(1, 1, 1), /**< IN with pull-up */
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GPIO_OUT = GPIO_MODE(0, 0, 0), /**< OUT (push-pull) */
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GPIO_OD = 0xfe, /**< not supported by HW */
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GPIO_OD_PU = 0xff /**< not supported by HW */
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} gpio_mode_t;
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/**
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* @brief Override active flank configuration values
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* @{
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*/
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#define HAVE_GPIO_FLANK_T
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typedef enum {
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GPIO_FALLING = 2, /**< emit interrupt on falling flank */
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GPIO_RISING = 1, /**< emit interrupt on rising flank */
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GPIO_BOTH = 3 /**< emit interrupt on both flanks */
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} gpio_flank_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief Available MUX values for configuring a pin's alternate function
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*/
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typedef enum {
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GPIO_MUX_A = 0x0, /**< select peripheral function A */
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GPIO_MUX_B = 0x1, /**< select peripheral function B */
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GPIO_MUX_C = 0x2, /**< select peripheral function C */
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GPIO_MUX_D = 0x3, /**< select peripheral function D */
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GPIO_MUX_E = 0x4, /**< select peripheral function E */
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GPIO_MUX_F = 0x5, /**< select peripheral function F */
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GPIO_MUX_G = 0x6, /**< select peripheral function G */
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GPIO_MUX_H = 0x7, /**< select peripheral function H */
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} gpio_mux_t;
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/**
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* @brief Available values for SERCOM UART RX pad selection
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*/
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typedef enum {
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UART_PAD_RX_0 = 0x0, /**< use pad 0 for RX line */
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UART_PAD_RX_1 = 0x1, /**< select pad 1 */
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UART_PAD_RX_2 = 0x2, /**< select pad 2 */
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UART_PAD_RX_3 = 0x3, /**< select pad 3 */
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} uart_rxpad_t;
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/**
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* @brief Available values for SERCOM UART TX pad selection
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*/
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typedef enum {
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UART_PAD_TX_0 = 0x0, /**< select pad 0 */
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UART_PAD_TX_2 = 0x1, /**< select pad 2 */
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UART_PAD_TX_0_RTS_2_CTS_3 = 0x2, /**< TX is pad 0, on top RTS on pad 2
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* and CTS on pad 3 */
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} uart_txpad_t;
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/**
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* @brief Available SERCOM UART flag selections
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*/
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typedef enum {
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UART_FLAG_NONE = 0x0, /**< No flags set */
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UART_FLAG_RUN_STANDBY = 0x1, /**< run SERCOM in standby mode */
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UART_FLAG_WAKEUP = 0x2, /**< wake from sleep on receive */
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} uart_flag_t;
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/**
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* @brief UART device configuration
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*/
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typedef struct {
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SercomUsart *dev; /**< pointer to the used UART device */
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gpio_t rx_pin; /**< pin used for RX */
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gpio_t tx_pin; /**< pin used for TX */
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gpio_mux_t mux; /**< alternative function for pins */
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uart_rxpad_t rx_pad; /**< pad selection for RX line */
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uart_txpad_t tx_pad; /**< pad selection for TX line */
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uart_flag_t flags; /**< set optional SERCOM flags */
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uint32_t gclk_src; /**< GCLK source which supplys SERCOM */
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} uart_conf_t;
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/**
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* @brief Available values for SERCOM SPI MISO pad selection
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*/
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typedef enum {
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SPI_PAD_MISO_0 = 0x0, /**< use pad 0 for MISO line */
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SPI_PAD_MISO_1 = 0x1, /**< use pad 0 for MISO line */
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SPI_PAD_MISO_2 = 0x2, /**< use pad 0 for MISO line */
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SPI_PAD_MISO_3 = 0x3, /**< use pad 0 for MISO line */
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} spi_misopad_t;
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/**
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* @brief Available values for SERCOM SPI MOSI and SCK pad selection
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*/
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typedef enum {
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SPI_PAD_MOSI_0_SCK_1 = 0x0, /**< use pad 0 for MOSI, pad 1 for SCK */
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SPI_PAD_MOSI_2_SCK_3 = 0x1, /**< use pad 2 for MOSI, pad 3 for SCK */
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SPI_PAD_MOSI_3_SCK_1 = 0x2, /**< use pad 3 for MOSI, pad 1 for SCK */
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SPI_PAD_MOSI_0_SCK_3 = 0x3, /**< use pad 0 for MOSI, pad 3 for SCK */
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} spi_mosipad_t;
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/**
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* @brief Override SPI modes
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* @{
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*/
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#define HAVE_SPI_MODE_T
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typedef enum {
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SPI_MODE_0 = 0x0, /**< CPOL=0, CPHA=0 */
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SPI_MODE_1 = 0x1, /**< CPOL=0, CPHA=1 */
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SPI_MODE_2 = 0x2, /**< CPOL=1, CPHA=0 */
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SPI_MODE_3 = 0x3 /**< CPOL=1, CPHA=1 */
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} spi_mode_t;
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/** @} */
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/**
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* @brief Override SPI clock speed values
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* @{
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*/
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#define HAVE_SPI_CLK_T
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typedef enum {
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SPI_CLK_100KHZ = 100000U, /**< drive the SPI bus with 100KHz */
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SPI_CLK_400KHZ = 400000U, /**< drive the SPI bus with 400KHz */
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SPI_CLK_1MHZ = 1000000U, /**< drive the SPI bus with 1MHz */
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SPI_CLK_5MHZ = 5000000U, /**< drive the SPI bus with 5MHz */
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SPI_CLK_10MHZ = 10000000U /**< drive the SPI bus with 10MHz */
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} spi_clk_t;
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/** @} */
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/**
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* @brief SPI device configuration
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*/
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typedef struct {
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SercomSpi *dev; /**< pointer to the used SPI device */
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gpio_t miso_pin; /**< used MISO pin */
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gpio_t mosi_pin; /**< used MOSI pin */
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gpio_t clk_pin; /**< used CLK pin */
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gpio_mux_t miso_mux; /**< alternate function for MISO pin (mux) */
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gpio_mux_t mosi_mux; /**< alternate function for MOSI pin (mux) */
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gpio_mux_t clk_mux; /**< alternate function for CLK pin (mux) */
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spi_misopad_t miso_pad; /**< pad to use for MISO line */
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spi_mosipad_t mosi_pad; /**< pad to use for MOSI and CLK line */
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} spi_conf_t;
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/** @} */
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/**
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* @brief Available SERCOM I2C flag selections
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*/
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typedef enum {
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I2C_FLAG_NONE = 0x0, /**< No flags set */
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I2C_FLAG_RUN_STANDBY = 0x1, /**< run SERCOM in standby mode */
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} i2c_flag_t;
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/**
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* @name Override I2C clock speed values
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* @{
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*/
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#define HAVE_I2C_SPEED_T
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typedef enum {
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I2C_SPEED_LOW = 10000U, /**< low speed mode: ~10kbit/s */
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I2C_SPEED_NORMAL = 100000U, /**< normal mode: ~100kbit/s */
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I2C_SPEED_FAST = 400000U, /**< fast mode: ~400kbit/s */
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I2C_SPEED_FAST_PLUS = 1000000U, /**< fast plus mode: ~1Mbit/s */
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I2C_SPEED_HIGH = 3400000U, /**< high speed mode: ~3.4Mbit/s */
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} i2c_speed_t;
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/** @} */
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/**
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* @brief I2C device configuration
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*/
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typedef struct {
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SercomI2cm *dev; /**< pointer to the used I2C device */
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i2c_speed_t speed; /**< baudrate used for the bus */
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gpio_t scl_pin; /**< used SCL pin */
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gpio_t sda_pin; /**< used MOSI pin */
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gpio_mux_t mux; /**< alternate function (mux) */
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uint8_t gclk_src; /**< GCLK source which supplys SERCOM */
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uint8_t flags; /**< allow SERCOM to run in standby mode */
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} i2c_conf_t;
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/**
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* @brief Set up alternate function (PMUX setting) for a PORT pin
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*
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* @param[in] pin Pin to set the multiplexing for
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* @param[in] mux Mux value
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*/
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void gpio_init_mux(gpio_t pin, gpio_mux_t mux);
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/**
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* @brief Return the numeric id of a SERCOM device derived from its address
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*
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* @param[in] sercom SERCOM device
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*
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* @return numeric id of the given SERCOM device
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*/
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static inline int sercom_id(void *sercom)
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{
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#if defined(CPU_FAM_SAMD21)
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return ((((uint32_t)sercom) >> 10) & 0x7) - 2;
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#elif defined(CPU_FAM_SAML21) || defined(CPU_FAM_SAMR30)
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/* Left side handles SERCOM0-4 while right side handles unaligned address of SERCOM5 */
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return ((((uint32_t)sercom) >> 10) & 0x7) + ((((uint32_t)sercom) >> 22) & 0x04);
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#endif
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}
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/**
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* @brief Enable peripheral clock for given SERCOM device
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*
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* @param[in] sercom SERCOM device
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*/
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static inline void sercom_clk_en(void *sercom)
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{
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#if defined(CPU_FAM_SAMD21)
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PM->APBCMASK.reg |= (PM_APBCMASK_SERCOM0 << sercom_id(sercom));
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#elif defined(CPU_FAM_SAML21) || defined(CPU_FAM_SAMR30)
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if (sercom_id(sercom) < 5) {
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MCLK->APBCMASK.reg |= (MCLK_APBCMASK_SERCOM0 << sercom_id(sercom));
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} else {
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MCLK->APBDMASK.reg |= (MCLK_APBDMASK_SERCOM5);
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}
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#endif
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}
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/**
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* @brief Disable peripheral clock for given SERCOM device
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*
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* @param[in] sercom SERCOM device
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*/
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static inline void sercom_clk_dis(void *sercom)
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{
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#if defined(CPU_FAM_SAMD21)
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PM->APBCMASK.reg &= ~(PM_APBCMASK_SERCOM0 << sercom_id(sercom));
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#elif defined(CPU_FAM_SAML21) || defined(CPU_FAM_SAMR30)
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if (sercom_id(sercom) < 5) {
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MCLK->APBCMASK.reg &= ~(MCLK_APBCMASK_SERCOM0 << sercom_id(sercom));
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} else {
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MCLK->APBDMASK.reg &= ~(MCLK_APBDMASK_SERCOM5);
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}
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#endif
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}
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/**
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* @brief Configure generator clock for given SERCOM device
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*
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* @param[in] sercom SERCOM device
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* @param[in] gclk Generator clock
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*/
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static inline void sercom_set_gen(void *sercom, uint32_t gclk)
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{
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#if defined(CPU_FAM_SAMD21)
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GCLK->CLKCTRL.reg = (GCLK_CLKCTRL_CLKEN | gclk |
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(SERCOM0_GCLK_ID_CORE + sercom_id(sercom)));
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while (GCLK->STATUS.reg & GCLK_STATUS_SYNCBUSY) {}
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#elif defined(CPU_FAM_SAML21) || defined(CPU_FAM_SAMR30)
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if (sercom_id(sercom) < 5) {
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GCLK->PCHCTRL[SERCOM0_GCLK_ID_CORE + sercom_id(sercom)].reg =
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(GCLK_PCHCTRL_CHEN | gclk);
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} else {
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GCLK->PCHCTRL[SERCOM5_GCLK_ID_CORE].reg =
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(GCLK_PCHCTRL_CHEN | gclk);
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}
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#endif
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}
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/**
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* @brief ADC Channel Configuration
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*/
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typedef struct {
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gpio_t pin; /**< ADC channel pin */
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uint32_t muxpos; /**< ADC channel pin multiplexer value */
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} adc_conf_chan_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_COMMON_H */
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/** @} */
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