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291 lines
13 KiB
C
291 lines
13 KiB
C
/******************************************************************************
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* Filename: hw_wdt_h
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* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017)
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* Revision: 48345
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_WDT_H__
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#define __HW_WDT_H__
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//*****************************************************************************
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//
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// This section defines the register offsets of
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// WDT component
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//
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//*****************************************************************************
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// Configuration
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#define WDT_O_LOAD 0x00000000
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// Current Count Value
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#define WDT_O_VALUE 0x00000004
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// Control
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#define WDT_O_CTL 0x00000008
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// Interrupt Clear
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#define WDT_O_ICR 0x0000000C
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// Raw Interrupt Status
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#define WDT_O_RIS 0x00000010
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// Masked Interrupt Status
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#define WDT_O_MIS 0x00000014
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// Test Mode
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#define WDT_O_TEST 0x00000418
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// Interrupt Cause Test Mode
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#define WDT_O_INT_CAUS 0x0000041C
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// Lock
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#define WDT_O_LOCK 0x00000C00
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//*****************************************************************************
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//
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// Register: WDT_O_LOAD
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//
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//*****************************************************************************
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// Field: [31:0] WDTLOAD
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//
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// This register is the 32-bit interval value used by the 32-bit counter. When
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// this register is written, the value is immediately loaded and the counter is
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// restarted to count down from the new value. If this register is loaded with
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// 0x0000.0000, an interrupt is immediately generated.
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#define WDT_LOAD_WDTLOAD_W 32
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#define WDT_LOAD_WDTLOAD_M 0xFFFFFFFF
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#define WDT_LOAD_WDTLOAD_S 0
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//*****************************************************************************
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//
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// Register: WDT_O_VALUE
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//
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//*****************************************************************************
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// Field: [31:0] WDTVALUE
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//
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// This register contains the current count value of the timer.
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#define WDT_VALUE_WDTVALUE_W 32
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#define WDT_VALUE_WDTVALUE_M 0xFFFFFFFF
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#define WDT_VALUE_WDTVALUE_S 0
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//*****************************************************************************
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//
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// Register: WDT_O_CTL
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//
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//*****************************************************************************
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// Field: [2] INTTYPE
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//
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// WDT Interrupt Type
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//
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// 0: WDT interrupt is a standard interrupt.
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// 1: WDT interrupt is a non-maskable interrupt.
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// ENUMs:
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// NONMASKABLE Non-maskable interrupt
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// MASKABLE Maskable interrupt
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#define WDT_CTL_INTTYPE 0x00000004
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#define WDT_CTL_INTTYPE_BITN 2
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#define WDT_CTL_INTTYPE_M 0x00000004
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#define WDT_CTL_INTTYPE_S 2
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#define WDT_CTL_INTTYPE_NONMASKABLE 0x00000004
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#define WDT_CTL_INTTYPE_MASKABLE 0x00000000
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// Field: [1] RESEN
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//
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// WDT Reset Enable. Defines the function of the WDT reset source (see
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// PRCM:WARMRESET.WDT_STAT if enabled)
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//
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// 0: Disabled.
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// 1: Enable the Watchdog reset output.
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// ENUMs:
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// EN Reset output Enabled
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// DIS Reset output Disabled
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#define WDT_CTL_RESEN 0x00000002
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#define WDT_CTL_RESEN_BITN 1
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#define WDT_CTL_RESEN_M 0x00000002
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#define WDT_CTL_RESEN_S 1
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#define WDT_CTL_RESEN_EN 0x00000002
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#define WDT_CTL_RESEN_DIS 0x00000000
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// Field: [0] INTEN
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//
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// WDT Interrupt Enable
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//
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// 0: Interrupt event disabled.
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// 1: Interrupt event enabled. Once set, this bit can only be cleared by a
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// hardware reset.
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// ENUMs:
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// EN Interrupt Enabled
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// DIS Interrupt Disabled
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#define WDT_CTL_INTEN 0x00000001
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#define WDT_CTL_INTEN_BITN 0
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#define WDT_CTL_INTEN_M 0x00000001
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#define WDT_CTL_INTEN_S 0
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#define WDT_CTL_INTEN_EN 0x00000001
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#define WDT_CTL_INTEN_DIS 0x00000000
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//*****************************************************************************
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//
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// Register: WDT_O_ICR
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//
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//*****************************************************************************
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// Field: [31:0] WDTICR
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//
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// This register is the interrupt clear register. A write of any value to this
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// register clears the WDT interrupt and reloads the 32-bit counter from the
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// LOAD register.
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#define WDT_ICR_WDTICR_W 32
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#define WDT_ICR_WDTICR_M 0xFFFFFFFF
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#define WDT_ICR_WDTICR_S 0
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//*****************************************************************************
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//
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// Register: WDT_O_RIS
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//
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//*****************************************************************************
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// Field: [0] WDTRIS
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//
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// This register is the raw interrupt status register. WDT interrupt events can
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// be monitored via this register if the controller interrupt is masked.
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//
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// Value Description
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//
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// 0: The WDT has not timed out
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// 1: A WDT time-out event has occurred
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//
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#define WDT_RIS_WDTRIS 0x00000001
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#define WDT_RIS_WDTRIS_BITN 0
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#define WDT_RIS_WDTRIS_M 0x00000001
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#define WDT_RIS_WDTRIS_S 0
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//*****************************************************************************
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//
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// Register: WDT_O_MIS
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//
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//*****************************************************************************
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// Field: [0] WDTMIS
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//
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// This register is the masked interrupt status register. The value of this
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// register is the logical AND of the raw interrupt bit and the WDT interrupt
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// enable bit CTL.INTEN.
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//
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// Value Description
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//
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// 0: The WDT has not timed out or is masked.
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// 1: An unmasked WDT time-out event has occurred.
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#define WDT_MIS_WDTMIS 0x00000001
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#define WDT_MIS_WDTMIS_BITN 0
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#define WDT_MIS_WDTMIS_M 0x00000001
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#define WDT_MIS_WDTMIS_S 0
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//*****************************************************************************
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//
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// Register: WDT_O_TEST
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//
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//*****************************************************************************
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// Field: [8] STALL
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//
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// WDT Stall Enable
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//
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// 0: The WDT timer continues counting if the CPU is stopped with a debugger.
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// 1: If the CPU is stopped with a debugger, the WDT stops counting. Once the
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// CPU is restarted, the WDT resumes counting.
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// ENUMs:
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// EN Enable STALL
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// DIS Disable STALL
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#define WDT_TEST_STALL 0x00000100
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#define WDT_TEST_STALL_BITN 8
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#define WDT_TEST_STALL_M 0x00000100
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#define WDT_TEST_STALL_S 8
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#define WDT_TEST_STALL_EN 0x00000100
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#define WDT_TEST_STALL_DIS 0x00000000
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// Field: [0] TEST_EN
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//
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// The test enable bit
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//
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// 0: Enable external reset
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// 1: Disables the generation of an external reset. Instead bit 1 of the
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// INT_CAUS register is set and an interrupt is generated
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// ENUMs:
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// EN Test mode Enabled
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// DIS Test mode Disabled
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#define WDT_TEST_TEST_EN 0x00000001
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#define WDT_TEST_TEST_EN_BITN 0
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#define WDT_TEST_TEST_EN_M 0x00000001
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#define WDT_TEST_TEST_EN_S 0
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#define WDT_TEST_TEST_EN_EN 0x00000001
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#define WDT_TEST_TEST_EN_DIS 0x00000000
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//*****************************************************************************
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//
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// Register: WDT_O_INT_CAUS
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//
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//*****************************************************************************
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// Field: [1] CAUSE_RESET
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//
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// Indicates that the cause of an interrupt was a reset generated but blocked
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// due to TEST.TEST_EN (only possible when TEST.TEST_EN is set).
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#define WDT_INT_CAUS_CAUSE_RESET 0x00000002
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#define WDT_INT_CAUS_CAUSE_RESET_BITN 1
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#define WDT_INT_CAUS_CAUSE_RESET_M 0x00000002
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#define WDT_INT_CAUS_CAUSE_RESET_S 1
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// Field: [0] CAUSE_INTR
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//
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// Replica of RIS.WDTRIS
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#define WDT_INT_CAUS_CAUSE_INTR 0x00000001
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#define WDT_INT_CAUS_CAUSE_INTR_BITN 0
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#define WDT_INT_CAUS_CAUSE_INTR_M 0x00000001
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#define WDT_INT_CAUS_CAUSE_INTR_S 0
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//*****************************************************************************
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//
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// Register: WDT_O_LOCK
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//
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//*****************************************************************************
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// Field: [31:0] WDTLOCK
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//
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// WDT Lock: A write of the value 0x1ACC.E551 unlocks the watchdog registers
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// for write access. A write of any other value reapplies the lock, preventing
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// any register updates (NOTE: TEST.TEST_EN bit is not lockable).
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//
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// A read of this register returns the following values:
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//
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// 0x0000.0000: Unlocked
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// 0x0000.0001: Locked
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#define WDT_LOCK_WDTLOCK_W 32
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#define WDT_LOCK_WDTLOCK_M 0xFFFFFFFF
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#define WDT_LOCK_WDTLOCK_S 0
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#endif // __WDT__
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