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There are some constraints to the oscillators on the samd5x. - DFLL is fixed to run at 48 MHz - DPLL can run at 96 to 200 MHz Always use DFLL for frequencies <= 48 MHz. For frequencies >= 96 MHz, use DPLL directly. For frequencies < 96 MHz, clock DPLL at twice the desired frequency and use a divider.
86 lines
2.5 KiB
C
86 lines
2.5 KiB
C
/*
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* Copyright (C) 2019 ML!PA Consulting GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_samd5x
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* @brief CPU specific definitions for internal peripheral handling
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Benjamin Valentin <benjamin.valentin@ml-pa.com>
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*/
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#include <limits.h>
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#include "periph_cpu_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief DFLL runs at at fixed frequency of 48 MHz
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*/
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#define SAM0_DFLL_FREQ_HZ (48000000U)
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/**
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* @brief DPLL must run with at least 96 MHz
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*/
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#define SAM0_DPLL_FREQ_MIN_HZ (96000000U)
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/**
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* @brief DPLL frequency must not exceed 200 MHz
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*/
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#define SAM0_DPLL_FREQ_MAX_HZ (200000000U)
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/**
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* @brief Mapping of pins to EXTI lines, -1 means not EXTI possible
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*/
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static const int8_t exti_config[4][32] = {
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#ifdef CPU_MODEL_SAMD51J20A
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{ 0, 1, 2, 3, 4, 5, 6, 7, -1, 9, 10, 11, 12, 13, 14, 15,
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, -1, 11, -1, -1, 14, 15 },
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{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
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0, 1, -1, -1, -1, -1, 6, 7, -1, -1, -1, -1, -1, -1, 14, 15 },
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
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{-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
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#elif CPU_MODEL_SAME54P20A
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{ 0, 1, 2, 3, 4, 5, 6, 7, -1, 9, 10, 11, 12, 13, 14, 15,
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, -1, 11, -1, -1, 14, 15 },
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{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 14, 15 },
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{ 0, 1, 2, 3, 4, 5, 6, 9, -1, -1, 10, 11, 12, 13, 14, 15,
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0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, -1, 14, 15 },
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{ 0, 1, -1, -1, -1, -1, -1, -1, 3, 4, 5, 6, 7, -1, -1, -1,
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-1, -1, -1, -1, 10, 11, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 }
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#else
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#error Please define a proper CPU_MODEL.
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#endif
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};
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/**
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* @brief Override SPI hardware chip select macro
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*
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* As of now, we do not support HW CS, so we always set it to a fixed value
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*/
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#define SPI_HWCS(x) (UINT_MAX - 1)
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_H */
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/** @} */
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