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https://github.com/RIOT-OS/RIOT.git
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133 lines
2.9 KiB
C
133 lines
2.9 KiB
C
/*
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* Copyright (C) 2014-2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_sam3
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* @ingroup drivers_periph_uart
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* @{
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*
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* @file
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* @brief Low-level UART driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include "cpu.h"
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#include "board.h"
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#include "periph/uart.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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/**
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* @brief Allocate memory to store the callback functions.
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*/
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static uart_isr_ctx_t ctx[UART_NUMOF];
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int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
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{
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Uart *dev;
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/* make sure given device is valid */
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if (uart >= UART_NUMOF) {
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return UART_NODEV;
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}
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/* get base register */
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dev = uart_config[uart].dev;
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/* register callback */
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ctx[uart].rx_cb = rx_cb;
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ctx[uart].arg = arg;
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/* enable clock */
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uart_poweron(uart);
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/* configure pins
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TODO: optimize once GPIO refactoring is merged */
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uart_config[uart].rx_port->PIO_PDR = (1 << uart_config[uart].rx_pin);
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uart_config[uart].rx_port->PIO_ABSR &= ~(1 << uart_config[uart].rx_pin);
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uart_config[uart].tx_port->PIO_ABSR |= (uart_config[uart].mux <<
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uart_config[uart].rx_pin);
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uart_config[uart].tx_port->PIO_PDR = (1 << uart_config[uart].tx_pin);
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uart_config[uart].tx_port->PIO_ABSR &= ~(1 << uart_config[uart].tx_pin);
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uart_config[uart].tx_port->PIO_ABSR |= (uart_config[uart].mux <<
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uart_config[uart].tx_pin);
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/* configure baud rate and set mode to 8N1 */
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dev->UART_BRGR = (CLOCK_CORECLOCK / (16 * baudrate));
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dev->UART_MR = UART_MR_PAR_NO | US_MR_CHRL_8_BIT;
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dev->UART_CR = UART_CR_RXEN | UART_CR_TXEN | UART_CR_RSTSTA;
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/* enable RX interrupt */
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NVIC_EnableIRQ(uart_config[uart].irqn);
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dev->UART_IER = UART_IER_RXRDY;
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return UART_OK;
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}
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void uart_write(uart_t uart, const uint8_t *data, size_t len)
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{
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Uart *dev = uart_config[uart].dev;
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for (size_t i = 0; i < len; i++) {
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while (!(dev->UART_SR & UART_SR_TXRDY)) {}
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dev->UART_THR = data[i];
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}
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}
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void uart_poweron(uart_t uart)
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{
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PMC->PMC_PCER0 |= (1 << uart_config[uart].pmc_id);
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}
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void uart_poweroff(uart_t uart)
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{
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PMC->PMC_PCER0 &= ~(1 << uart_config[uart].pmc_id);
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}
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static inline void isr_handler(int num)
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{
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Uart *dev = uart_config[num].dev;
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if (dev->UART_SR & UART_SR_RXRDY) {
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ctx[num].rx_cb(ctx[num].arg, (uint8_t)dev->UART_RHR);
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}
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cortexm_isr_end();
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}
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#ifdef UART_0_ISR
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void UART_0_ISR(void)
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{
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isr_handler(0);
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}
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#endif
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#ifdef UART_1_ISR
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void UART_1_ISR(void)
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{
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isr_handler(1);
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}
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#endif
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#ifdef UART_2_ISR
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void UART_2_ISR(void)
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{
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isr_handler(2);
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}
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#endif
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#ifdef UART_3_ISR
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void UART_3_ISR(void)
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{
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isr_handler(3);
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}
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#endif
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