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https://github.com/RIOT-OS/RIOT.git
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c0628a3058
add peripheral drivers for Freescale Kinetis MCUs:
adc driver
cpuid driver
gpio driver
hwtimer_arch driver (hwtimer used Low Power Timer)
i2c driver (master mode only)
mcg driver
pwm driver
random_rnga driver
random_rngb driver
rtc driver
spi driver
timer driver (timer used Periodic Interrupt Timer)
uart driver
add doc.txt (configuration examples)
random_rnga: Update RNGA driver in preparation for RNGB driver.
random_rngb: Add RNGB driver.
spi: refactor SPI to work for multiple CTARS, add spi_acquire, spi_release
gpio: Add gpio_irq_enable, gpio_irq_disable. Refactor GPIO.
gpio: Add gpio_irq_enable, gpio_irq_disable.
gpio: Refactor ISR functions to work with all GPIOs (0-31) and all ports (PORTA-PORTH)
adc: Refactor ADC, add calibration and scaling.
Added integer scaling of results in adc_map.
Handle precision setting in adc_init.
Set ADC clock divider depending on module clock.
Add ADC_1 as a possible device.
Add ADC calibration procedure according to K60 ref manual.
Handle ADC pins which are not part of the pin function mux.
Signed-off-by: Joakim Gebart <joakim.gebart@eistec.se>
427 lines
11 KiB
C
427 lines
11 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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* Copyright (C) 2014 PHYTEC Messtechnik GmbH
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* Copyright (C) 2015 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_kinetis_common_adc
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* @{
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*
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* @file
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* @brief Low-level ADC driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Johann Fischer <j.fischer@phytec.de>
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* @author Jonas Remmert <j.remmert@phytec.de>
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* @author Joakim Gebart <joakim.gebart@eistec.se>
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*
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* @}
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*/
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#include <stdio.h>
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#include "cpu.h"
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#include "periph/adc.h"
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#include "periph_conf.h"
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/* guard in case that no ADC device is defined */
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#if ADC_NUMOF
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typedef struct {
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int max_value;
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int bits;
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} adc_config_t;
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adc_config_t adc_config[ADC_NUMOF];
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/**
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* @brief Perform ADC calibration routine.
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*
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* This is a recipe taken straight from the Kinetis K60 reference manual. It has
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* been tested on MK60DN512VLL10.
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*
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* @param[in] ADC_ptr Pointer to ADC device to operate on.
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*
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* @return 0 on success
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* @return <0 on errors
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*/
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int kinetis_adc_calibrate(ADC_Type *ADC_ptr)
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{
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uint16_t cal;
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ADC_ptr->SC3 |= ADC_SC3_CAL_MASK;
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while (ADC_ptr->SC3 & ADC_SC3_CAL_MASK); /* wait for calibration to finish */
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while (!(ADC_ptr->SC1[0] & ADC_SC1_COCO_MASK));
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if (ADC_ptr->SC3 & ADC_SC3_CALF_MASK) {
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/* calibration failed for some reason, possibly SC2[ADTRG] is 1 ? */
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return -1;
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}
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/*
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* Following the steps in the reference manual:
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*/
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/* 1. Initialize or clear a 16-bit variable in RAM. */
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/* 2. Add the plus-side calibration results CLP0, CLP1, CLP2, CLP3, CLP4, and
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* CLPS to the variable. */
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cal = ADC_ptr->CLP0 + ADC_ptr->CLP1 + ADC_ptr->CLP2 + ADC_ptr->CLP3 +
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ADC_ptr->CLP4 + ADC_ptr->CLPS;
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/* 3. Divide the variable by two. */
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cal /= 2;
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/* 4. Set the MSB of the variable. */
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cal |= (1 << 15);
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/* (5. The previous two steps can be achieved by setting the carry bit,
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* rotating to the right through the carry bit on the high byte and again on
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* the low byte.)
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* We ignore the above optimization suggestion, we most likely only perform
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* this calibration on startup and it will only save nanoseconds. */
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/* 6. Store the value in the plus-side gain calibration register PG. */
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ADC_ptr->PG = cal;
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/* 7. Repeat the procedure for the minus-side gain calibration value. */
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cal = ADC_ptr->CLM0 + ADC_ptr->CLM1 + ADC_ptr->CLM2 + ADC_ptr->CLM3 +
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ADC_ptr->CLM4 + ADC_ptr->CLMS;
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cal /= 2;
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cal |= (1 << 15);
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ADC_ptr->MG = cal;
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return 0;
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}
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int adc_init(adc_t dev, adc_precision_t precision)
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{
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ADC_Type *adc = 0;
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PORT_Type *port[ADC_MAX_CHANNELS];
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uint8_t pins[ADC_MAX_CHANNELS];
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uint8_t af[ADC_MAX_CHANNELS];
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int channels = 0;
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uint32_t mode = 0;
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uint32_t div = 0;
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int i = 0;
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uint32_t clock = 0;
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adc_poweron(dev);
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switch (dev) {
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#if ADC_0_EN
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case ADC_0:
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adc = ADC_0_DEV;
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port[0] = ADC_0_CH0_PORT;
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port[1] = ADC_0_CH1_PORT;
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port[2] = ADC_0_CH2_PORT;
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port[3] = ADC_0_CH3_PORT;
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port[4] = ADC_0_CH4_PORT;
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port[5] = ADC_0_CH5_PORT;
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pins[0] = ADC_0_CH0_PIN;
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pins[1] = ADC_0_CH1_PIN;
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pins[2] = ADC_0_CH2_PIN;
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pins[3] = ADC_0_CH3_PIN;
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pins[4] = ADC_0_CH4_PIN;
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pins[5] = ADC_0_CH5_PIN;
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af[0] = ADC_0_CH0_PIN_AF;
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af[1] = ADC_0_CH1_PIN_AF;
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af[2] = ADC_0_CH2_PIN_AF;
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af[3] = ADC_0_CH3_PIN_AF;
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af[4] = ADC_0_CH4_PIN_AF;
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af[5] = ADC_0_CH5_PIN_AF;
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channels = ADC_0_CHANNELS;
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clock = ADC_0_MODULE_CLOCK;
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ADC_0_PORT_CLKEN();
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break;
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#endif
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#if ADC_1_EN
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case ADC_1:
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adc = ADC_1_DEV;
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port[0] = ADC_1_CH0_PORT;
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port[1] = ADC_1_CH1_PORT;
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port[2] = ADC_1_CH2_PORT;
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port[3] = ADC_1_CH3_PORT;
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port[4] = ADC_1_CH4_PORT;
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port[5] = ADC_1_CH5_PORT;
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pins[0] = ADC_1_CH0_PIN;
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pins[1] = ADC_1_CH1_PIN;
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pins[2] = ADC_1_CH2_PIN;
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pins[3] = ADC_1_CH3_PIN;
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pins[4] = ADC_1_CH4_PIN;
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pins[5] = ADC_1_CH5_PIN;
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af[0] = ADC_1_CH0_PIN_AF;
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af[1] = ADC_1_CH1_PIN_AF;
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af[2] = ADC_1_CH2_PIN_AF;
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af[3] = ADC_1_CH3_PIN_AF;
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af[4] = ADC_1_CH4_PIN_AF;
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af[5] = ADC_1_CH5_PIN_AF;
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channels = ADC_1_CHANNELS;
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clock = ADC_1_MODULE_CLOCK;
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ADC_1_PORT_CLKEN();
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break;
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#endif
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default:
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return -1;
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}
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if (channels > ADC_MAX_CHANNELS) {
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return -1;
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}
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/* set precision, these numbers are valid for the K60 */
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switch (precision) {
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case ADC_RES_6BIT:
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/* Not supported by hardware, use 8 bit mode. */
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mode = ADC_CFG1_MODE(0);
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adc_config[dev].bits = 8;
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break;
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case ADC_RES_8BIT:
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mode = ADC_CFG1_MODE(0);
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adc_config[dev].bits = 8;
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break;
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case ADC_RES_10BIT:
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mode = ADC_CFG1_MODE(2);
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adc_config[dev].bits = 10;
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break;
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case ADC_RES_12BIT:
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mode = ADC_CFG1_MODE(1);
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adc_config[dev].bits = 12;
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break;
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case ADC_RES_14BIT:
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/* Not supported by hardware, use 16 bit mode. */
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mode = ADC_CFG1_MODE(3);
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adc_config[dev].bits = 16;
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break;
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case ADC_RES_16BIT:
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mode = ADC_CFG1_MODE(3);
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adc_config[dev].bits = 16;
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break;
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}
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adc_config[dev].max_value = (1 << adc_config[dev].bits) - 1;
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for (i = 0; i < channels; i++) {
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/* Check whether we need to set the pin mux for this channel. */
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if (port[i] != NULL) {
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port[i]->PCR[pins[i]] = PORT_PCR_MUX(af[i]);
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}
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}
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/* The ADC requires at least 2 MHz module clock for full accuracy, and less
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* than 12 MHz */
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/* For the calibration it is important that the ADC clock is <= 4 MHz */
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if (clock > 4000000 * 8) {
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/* Need to divide by 16, we set the clock input to BusClock/2 and
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* divide clock by 8 (the maximum divider) */
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div = ADC_CFG1_ADIV(3) | ADC_CFG1_ADICLK(1);
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}
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else if (clock > 4000000 * 4) {
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/* divide clock by 8 */
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div = ADC_CFG1_ADIV(3);
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}
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else if (clock > 4000000 * 2) {
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/* divide clock by 4 */
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div = ADC_CFG1_ADIV(2);
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}
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else if (clock > 4000000 * 1) {
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/* divide clock by 2 */
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div = ADC_CFG1_ADIV(1);
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}
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else {
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/* no clock divider */
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div = ADC_CFG1_ADIV(0);
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}
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/* set configuration register 1: clocking and precision */
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/* Set long sample time */
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adc->CFG1 = ADC_CFG1_ADLSMP_MASK | mode | div;
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/* select ADxxb channels, longest sample time (20 extra ADC cycles) */
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adc->CFG2 = ADC_CFG2_MUXSEL_MASK | ADC_CFG2_ADLSTS(0);
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/* select software trigger, external ref pins */
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adc->SC2 = ADC_SC2_REFSEL(0);
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/* select hardware average over 32 samples */
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adc->SC3 = ADC_SC3_AVGE_MASK | ADC_SC3_AVGS(3);
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/* set an (arbitrary) input channel, single-ended mode */
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adc->SC1[0] = ADC_SC1_ADCH(ADC_0_CH0);
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adc->SC1[1] = ADC_SC1_ADCH(ADC_0_CH0);
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/* perform calibration routine */
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if (kinetis_adc_calibrate(adc) != 0) {
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return -1;
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}
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return 0;
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}
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int adc_sample(adc_t dev, int channel)
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{
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ADC_Type *adc = 0;
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switch (dev) {
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#if ADC_0_EN
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case ADC_0:
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adc = ADC_0_DEV;
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/* start single conversion on corresponding channel */
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switch (channel) {
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case 0:
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adc->SC1[0] = ADC_SC1_ADCH(ADC_0_CH0);
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break;
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case 1:
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adc->SC1[0] = ADC_SC1_ADCH(ADC_0_CH1);
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break;
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case 2:
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adc->SC1[0] = ADC_SC1_ADCH(ADC_0_CH2);
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break;
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case 3:
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adc->SC1[0] = ADC_SC1_ADCH(ADC_0_CH3);
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break;
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case 4:
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adc->SC1[0] = ADC_SC1_ADCH(ADC_0_CH4);
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break;
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case 5:
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adc->SC1[0] = ADC_SC1_ADCH(ADC_0_CH5);
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break;
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default:
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return -1;
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}
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break;
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#endif
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#if ADC_1_EN
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case ADC_1:
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adc = ADC_1_DEV;
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/* start single conversion on corresponding channel */
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switch (channel) {
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case 0:
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adc->SC1[0] = ADC_SC1_ADCH(ADC_1_CH0);
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break;
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case 1:
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adc->SC1[0] = ADC_SC1_ADCH(ADC_1_CH1);
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break;
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case 2:
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adc->SC1[0] = ADC_SC1_ADCH(ADC_1_CH2);
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break;
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case 3:
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adc->SC1[0] = ADC_SC1_ADCH(ADC_1_CH3);
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break;
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case 4:
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adc->SC1[0] = ADC_SC1_ADCH(ADC_1_CH4);
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break;
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case 5:
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adc->SC1[0] = ADC_SC1_ADCH(ADC_1_CH5);
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break;
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default:
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return -1;
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}
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break;
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#endif
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}
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/* wait until conversion is complete */
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/* TODO: Use interrupts and yield the thread */
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while (!(adc->SC1[0] & ADC_SC1_COCO_MASK));
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/* read and return result */
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return (int)adc->R[0];
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}
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void adc_poweron(adc_t dev)
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{
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switch (dev) {
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#if ADC_0_EN
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case ADC_0:
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ADC_0_CLKEN();
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break;
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#endif
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#if ADC_1_EN
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case ADC_1:
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ADC_1_CLKEN();
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break;
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#endif
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}
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}
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void adc_poweroff(adc_t dev)
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{
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switch (dev) {
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#if ADC_0_EN
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case ADC_0:
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ADC_0_CLKDIS();
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break;
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#endif
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#if ADC_1_EN
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case ADC_1:
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ADC_1_CLKDIS();
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break;
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#endif
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}
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}
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int adc_map(adc_t dev, int value, int min, int max)
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{
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int scale = max - min;
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/* NB: There is additional room for the multiplication result if using the
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* actual precision setting of the ADC as the limit in this if statement: */
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if (scale < (1 << 16)) {
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/* The ADCs on these CPUs are limited to 16 bits, the result of
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* value x scale will be 31 bits long or less. We use the upper part
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* of a 32 bit word when scaling */
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int32_t tmp = value * scale;
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/* Divide by ADC range to get the scaled result */
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return (tmp / (1 << adc_config[dev].bits));
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}
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else {
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/* Target scale is too large to use int32_t as an in between result */
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int64_t tmp = scale;
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/* Make sure the compiler does not generate code which will truncate the
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* result. */
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tmp *= value;
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/* Divide by ADC range to get the scaled result */
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tmp /= (1 << adc_config[dev].bits);
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return tmp;
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}
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}
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float adc_mapf(adc_t dev, int value, float min, float max)
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{
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return ((max - min) / ((float)adc_config[dev].max_value)) * value;
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}
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#endif /* ADC_NUMOF */
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