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7d1d5e77d8
New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
31 lines
812 B
C
31 lines
812 B
C
// See LICENSE for license details.
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#ifndef PLIC_H
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#define PLIC_H
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// 32 bits per source
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#define PLIC_PRIORITY_OFFSET (0x0000)
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#define PLIC_PRIORITY_SHIFT_PER_SOURCE 2
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// 1 bit per source (1 address)
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#define PLIC_PENDING_OFFSET (0x1000)
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#define PLIC_PENDING_SHIFT_PER_SOURCE 0
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//0x80 per target
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#define PLIC_ENABLE_OFFSET (0x2000)
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#define PLIC_ENABLE_SHIFT_PER_TARGET 7
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#define PLIC_THRESHOLD_OFFSET (0x200000)
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#define PLIC_CLAIM_OFFSET (0x200004)
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#define PLIC_THRESHOLD_SHIFT_PER_TARGET 12
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#define PLIC_CLAIM_SHIFT_PER_TARGET 12
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#define PLIC_MAX_SOURCE 1023
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#define PLIC_SOURCE_MASK 0x3FF
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#define PLIC_MAX_TARGET 15871
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#define PLIC_TARGET_MASK 0x3FFF
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#endif /* PLIC_H */
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