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143 lines
4.1 KiB
C
143 lines
4.1 KiB
C
/*
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* Copyright (C) 2016 Freie Universität Berlin
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* 2017 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief UART CPU specific definitions for the STM32 family
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Vincent Dupont <vincent@otakeys.com>
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*/
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#ifndef PERIPH_CPU_UART_H
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#define PERIPH_CPU_UART_H
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#include <stdint.h>
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#include "cpu.h"
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#include "periph/cpu_dma.h"
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#include "periph/cpu_gpio.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief UART hardware module types
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*/
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typedef enum {
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STM32_USART, /**< STM32 USART module type */
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STM32_LPUART, /**< STM32 Low-power UART (LPUART) module type */
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} uart_type_t;
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/**
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* @brief Size of the UART TX buffer for non-blocking mode.
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*/
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#ifndef UART_TXBUF_SIZE
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#define UART_TXBUF_SIZE (64)
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#endif
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#ifndef DOXYGEN
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/**
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* @brief Invalid UART mode mask
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*
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* This mask is also used to force data_bits_t to be uint32_t type
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* since it may be assigned a uint32_t variable in uart_mode
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*/
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#define UART_INVALID_MODE (0x8000000)
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/**
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* @brief Override parity values
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* @{
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*/
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#define HAVE_UART_PARITY_T
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typedef enum {
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UART_PARITY_NONE = 0, /**< no parity */
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UART_PARITY_EVEN = USART_CR1_PCE, /**< even parity */
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UART_PARITY_ODD = (USART_CR1_PCE | USART_CR1_PS), /**< odd parity */
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UART_PARITY_MARK = UART_INVALID_MODE | 4, /**< not supported */
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UART_PARITY_SPACE = UART_INVALID_MODE | 5 /**< not supported */
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} uart_parity_t;
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/** @} */
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/**
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* @brief Override data bits length values
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* @{
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*/
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#define HAVE_UART_DATA_BITS_T
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typedef enum {
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UART_DATA_BITS_5 = UART_INVALID_MODE | 1, /**< not supported */
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UART_DATA_BITS_6 = UART_INVALID_MODE | 2, /**< not supported unless parity is set */
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#if defined(USART_CR1_M1)
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UART_DATA_BITS_7 = USART_CR1_M1, /**< 7 data bits */
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#else
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UART_DATA_BITS_7 = UART_INVALID_MODE | 3, /**< not supported unless parity is set */
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#endif
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UART_DATA_BITS_8 = 0, /**< 8 data bits */
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} uart_data_bits_t;
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/** @} */
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/**
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* @brief Override stop bits length values
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* @{
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*/
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#define HAVE_UART_STOP_BITS_T
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typedef enum {
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UART_STOP_BITS_1 = 0, /**< 1 stop bit */
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UART_STOP_BITS_2 = USART_CR2_STOP_1, /**< 2 stop bits */
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} uart_stop_bits_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief Structure for UART configuration data
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*/
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typedef struct {
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USART_TypeDef *dev; /**< UART device base register address */
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uint32_t rcc_mask; /**< bit in clock enable register */
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gpio_t rx_pin; /**< RX pin */
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gpio_t tx_pin; /**< TX pin */
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#ifndef CPU_FAM_STM32F1
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gpio_af_t rx_af; /**< alternate function for RX pin */
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gpio_af_t tx_af; /**< alternate function for TX pin */
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#endif
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uint8_t bus; /**< APB bus */
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uint8_t irqn; /**< IRQ channel */
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#ifdef MODULE_PERIPH_UART_HW_FC
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gpio_t cts_pin; /**< CTS pin - set to GPIO_UNDEF when not using HW flow control */
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gpio_t rts_pin; /**< RTS pin */
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#ifndef CPU_FAM_STM32F1
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gpio_af_t cts_af; /**< alternate function for CTS pin */
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gpio_af_t rts_af; /**< alternate function for RTS pin */
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#endif
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#endif
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#if defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L4) || \
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defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
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defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
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defined(CPU_FAM_STM32MP1) || defined(CPU_FAM_STM32WL)
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uart_type_t type; /**< hardware module type (USART or LPUART) */
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uint32_t clk_src; /**< clock source used for UART */
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#endif
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#ifdef MODULE_PERIPH_DMA
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dma_t dma; /**< Logical DMA stream used for TX */
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uint8_t dma_chan; /**< DMA channel used for TX */
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#endif
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} uart_conf_t;
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_UART_H */
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/** @} */
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