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101 lines
3.1 KiB
C
101 lines
3.1 KiB
C
/*
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* Copyright (C) 2023 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief CPU specific definitions for SDIO/SDMMC for the STM32 family
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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*/
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#ifndef PERIPH_CPU_SDMMC_H
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#define PERIPH_CPU_SDMMC_H
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#include <stdint.h>
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#include "periph/cpu_dma.h"
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#include "periph/cpu_gpio.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Declare the types for SDIO/SDMMC only if the STM32 has SDIO/SDMMC peripheral */
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#if defined(SDMMC_POWER_PWRCTRL) || defined(SDIO_POWER_PWRCTRL)
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/* For F1, F2, F4 and L1 the SDMMC interface is called SDIO, define used
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* symbols for source code compatibility */
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#if !defined(SDMMC1) && !DOXYGEN
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#define SDMMC_TypeDef SDIO_TypeDef
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#endif
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/**
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* @brief SDIO/SDMMC buffers alignment because of STM32 DMA/FIFO restrictions
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*/
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#define SDMMC_CPU_DMA_ALIGNMENT 4
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/**
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* @brief SDIO/SDMMC buffer instantiation requirement for STM32
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*/
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#define SDMMC_CPU_DMA_REQUIREMENTS __attribute__((aligned(SDMMC_CPU_DMA_ALIGNMENT)))
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/**
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* @brief SDIO/SDMMC pin structure for STM32
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*/
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typedef struct {
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gpio_t pin; /**< GPIO pin */
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#ifndef CPU_FAM_STM32F1
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gpio_af_t af; /**< GPIO alternate function */
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#endif
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} sdmmc_pin_t;
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/**
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* @brief SDIO/SDMCC peripheral configuration for STM32
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*
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* To use 1-bit bus width, define `dat1` to `dat3` as `GPIO_UNDEF`. 8-bit bus
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* width with `dat4` to `dat7` is only available if the board provides
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* feature `periph_sdmmc_8bit`.
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*/
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typedef struct {
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SDMMC_TypeDef *dev; /**< SDIO/SDMMC device */
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uint8_t bus; /**< APB/AHB bus used for SDIO/SDMMC peripheral */
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uint32_t rcc_mask; /**< Bit mask in clock enable register */
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gpio_t cd; /**< Card Detect pin (GPIO_UNDEF if not used) */
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int cd_active; /**< Card Detect pin active level */
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gpio_mode_t cd_mode; /**< Card Detect pin mode */
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sdmmc_pin_t clk; /**< Clock pin */
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sdmmc_pin_t cmd; /**< Command/Response pin */
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sdmmc_pin_t dat0; /**< Data Line Bit 0 pin */
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sdmmc_pin_t dat1; /**< Data Line Bit 1 pin */
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sdmmc_pin_t dat2; /**< Data Line Bit 2 pin */
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sdmmc_pin_t dat3; /**< Data Line Bit 3 pin */
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#if IS_USED(MODULE_PERIPH_SDMMC_8BIT)
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sdmmc_pin_t dat4; /**< Data Line Bit 4 pin */
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sdmmc_pin_t dat5; /**< Data Line Bit 5 pin */
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sdmmc_pin_t dat6; /**< Data Line Bit 6 pin */
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sdmmc_pin_t dat7; /**< Data Line Bit 7 pin */
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#endif
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#if IS_USED(MODULE_PERIPH_DMA)
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dma_t dma; /**< Logical DMA stream used for SDIO/SDMMC */
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uint8_t dma_chan; /**< DMA channel used for SDIO/SDMMC */
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#endif
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uint8_t irqn; /**< SDIO/SDMMC interrupt number */
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} sdmmc_conf_t;
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#endif /* defined(SDMMC_POWER_PWRCTRL) || defined(SDIO_POWER_PWRCTRL) */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_SDMMC_H */
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/** @} */
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