mirror of
https://github.com/RIOT-OS/RIOT.git
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73ede74cd8
- removed neccessity to define empty `DAC_NUMOF 0` for each STM base board - adapted all board configs to this - joined stm32f2 to use common DAC driver - improved code of DAC driver
141 lines
3.4 KiB
C
141 lines
3.4 KiB
C
/*
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* Copyright (C) 2017 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo144-f746
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo144-f746 board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 216MHz, min: 96MHz, must be multiple of 24MHz */
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#define CLOCK_CORECLOCK (216000000U)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* min 25MHz */
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM2,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.bus = APB1,
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.irqn = TIM2_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim2
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART3,
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.rcc_mask = RCC_APB1ENR_USART3EN,
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.rx_pin = GPIO_PIN(PORT_D, 9),
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.tx_pin = GPIO_PIN(PORT_D, 8),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART3_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 6,
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.dma_chan = 4
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#endif
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},
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{
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.dev = USART6,
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.rcc_mask = RCC_APB2ENR_USART6EN,
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.rx_pin = GPIO_PIN(PORT_G, 9),
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.tx_pin = GPIO_PIN(PORT_G, 14),
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.rx_af = GPIO_AF8,
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.tx_af = GPIO_AF8,
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.bus = APB2,
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.irqn = USART6_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 5,
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.dma_chan = 4
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#endif
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},
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_D, 6),
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.tx_pin = GPIO_PIN(PORT_D, 5),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 4,
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.dma_chan = 4
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#endif
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}
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};
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#define UART_0_ISR (isr_usart3)
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#define UART_0_DMA_ISR (isr_dma1_stream6)
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#define UART_1_ISR (isr_usart6)
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#define UART_1_DMA_ISR (isr_dma1_stream5)
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#define UART_2_ISR (isr_usart2)
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#define UART_2_DMA_ISR (isr_dma1_stream4)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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#define ADC_NUMOF (0)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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