mirror of
https://github.com/RIOT-OS/RIOT.git
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154 lines
4.4 KiB
C
154 lines
4.4 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup boards_iotlab-m3
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the iotlab-m3 board
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*
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef PERIPH_CONF_H_
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#define PERIPH_CONF_H_
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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**/
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#define CLOCK_HSE (16000000U) /* frequency of external oscillator */
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#define CLOCK_CORECLOCK (72000000U) /* targeted core clock frequency */
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/* configuration of PLL prescaler and multiply values */
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/* CORECLOCK := HSE / PLL_HSE_DIV * PLL_HSE_MUL */
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#define CLOCK_PLL_HSE_DIV RCC_CFGR_PLLXTPRE_HSE_DIV2
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#define CLOCK_PLL_HSE_MUL RCC_CFGR_PLLMULL9
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/* configuration of peripheral bus clock prescalers */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 72MHz */
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 72MHz */
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* APB1 clock -> 36MHz */
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/* configuration of flash access cycles */
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_2
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/** @} */
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/**
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* @brief Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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/* device, APB bus, rcc_bit */
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{ TIM2, APB1, RCC_APB1ENR_TIM2EN, TIM2_IRQn },
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{ TIM3, APB1, RCC_APB1ENR_TIM3EN, TIM3_IRQn }
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};
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#define TIMER_0_ISR isr_tim2
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#define TIMER_1_ISR isr_tim3
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @brief UART configuration
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* @{
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*/
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#define UART_NUMOF (1U)
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#define UART_0_EN 1
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#define UART_1_EN 0
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#define UART_IRQ_PRIO 1
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/* UART 0 device configuration */
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#define UART_0_DEV USART1
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#define UART_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_USART1EN)
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#define UART_0_IRQ USART1_IRQn
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#define UART_0_ISR isr_usart1
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#define UART_0_BUS_FREQ 72000000
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/* UART 0 pin configuration */
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#define UART_0_RX_PIN GPIO_PIN(PORT_A,10)
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#define UART_0_TX_PIN GPIO_PIN(PORT_A,9)
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/* UART 1 device configuration */
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#define UART_1_DEV USART2
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#define UART_1_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
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#define UART_1_IRQ USART2_IRQn
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#define UART_1_ISR isr_usart2
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#define UART_1_BUS_FREQ 36000000
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/* UART 1 pin configuration */
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#define UART_1_RX_PIN GPIO_PIN(PORT_A,3)
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#define UART_1_TX_PIN GPIO_PIN(PORT_A,2)
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/** @} */
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/**
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* @brief SPI configuration
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* @{
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*/
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#define SPI_NUMOF (1U)
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#define SPI_0_EN 1
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/* SPI 0 device configuration */
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#define SPI_0_DEV SPI1
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#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
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#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
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#define SPI_0_BUS_DIV 1 /* 1 -> SPI runs with full CPU clock, 0 -> half CPU clock */
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/* SPI 0 pin configuration */
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#define SPI_0_CLK_PIN GPIO_PIN(PORT_A,5)
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#define SPI_0_MOSI_PIN GPIO_PIN(PORT_A,7)
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#define SPI_0_MISO_PIN GPIO_PIN(PORT_A,6)
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/** @} */
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/**
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* @name Real time counter configuration
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* @{
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*/
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#define RTT_NUMOF (1U)
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#define RTT_IRQ_PRIO 1
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#define RTT_DEV RTC
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#define RTT_IRQ RTC_IRQn
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#define RTT_ISR isr_rtc
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#define RTT_MAX_VALUE (0xffffffff)
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#define RTT_FREQUENCY (1) /* in Hz */
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#define RTT_PRESCALER (0x7fff) /* run with 1 Hz */
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (1U)
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#define I2C_0_EN 1
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#define I2C_IRQ_PRIO 1
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#define I2C_APBCLK (36000000U)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C1
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#define I2C_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_I2C1EN)
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#define I2C_0_CLKDIS() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
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#define I2C_0_EVT_IRQ I2C1_EV_IRQn
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#define I2C_0_EVT_ISR isr_i2c1_ev
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#define I2C_0_ERR_IRQ I2C1_ER_IRQn
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#define I2C_0_ERR_ISR isr_i2c1_er
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/* I2C 0 pin configuration */
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#define I2C_0_SCL_PIN GPIO_PIN(PORT_B,6)
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#define I2C_0_SDA_PIN GPIO_PIN(PORT_B,7)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H_ */
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/** @} */
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