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32bbba2fc5
lpc23xx has 2k of battery RAM that is retained in Deep Power Down mode. To not overwrite that data it must only be initialized on Power On Reset. However, RSIR looks the same when waking up from Deep Power Down as it does on the power-on case. So use 4 bytes of the backup RAM to keep a signature that is only valid if memory was retained (no power-on Reset). A small change to the linker script is required so two sections can be placed into flash.
76 lines
1.5 KiB
C
76 lines
1.5 KiB
C
/*
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* Copyright (C) 2013, Freie Universitaet Berlin (FUB). All rights reserved.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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#ifndef CPU_H
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#define CPU_H
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/**
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* @defgroup cpu_lpc2387 NXP LPC2387
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* @ingroup cpu
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* @brief NXP LPC2387 specific code
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* @{
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*/
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#include <stdio.h>
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#include <stdbool.h>
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#include "lpc2387.h"
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#include "arm_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern uintptr_t __stack_start; /**< end of user stack memory space */
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/**
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* @brief Scale lpc2387 cpu speed
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*/
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void lpc2387_pclk_scale(uint32_t source, uint32_t target, uint32_t *pclksel, uint32_t *prescale);
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/**
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* @brief Initialize lpc2387 cpu clocks
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*/
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void cpu_init_clks(void);
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/**
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* @brief install lpc2387 irq
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*/
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bool install_irq(int IntNumber, void (*HandlerAddr)(void), int Priority);
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#ifdef MODULE_PERIPH
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void gpio_init_ports(void);
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#endif
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/**
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* @brief Prints the current content of the link register (lr)
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*/
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static inline void cpu_print_last_instruction(void)
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{
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register uint32_t *lr_ptr;
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__asm__ __volatile__("mov %0, lr" : "=r"(lr_ptr));
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printf("%p\n", (void*) lr_ptr);
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}
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/**
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* @brief Returns true if the CPU woke from Deep Sleep
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*/
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bool cpu_woke_from_backup(void);
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/**
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* @brief The CPU has RAM that is retained in the deepest sleep mode.
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*/
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#define CPU_HAS_BACKUP_RAM (1)
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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#endif /* CPU_H */
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