mirror of
https://github.com/RIOT-OS/RIOT.git
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05f114d0af
- most were trivial
- missing group close or open
- extra space
- no doxygen comment
- name commad might open an implicit group
this hould also be implicit cosed but does not happen somtimes
- crazy: internal declared groups have to be closed internal
189 lines
4.6 KiB
C
189 lines
4.6 KiB
C
/*
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* Copyright (C) 2014 Hamburg University of Applied Sciences
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup drivers_nrf24l01p
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* @{
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*
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* @file
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* @brief Low-level driver for nrf24l01+ transceiver
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Peter Kietzmann <peter.kietzmann@haw-hamburg.de>
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*
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*/
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#ifndef NRF24L01P_SETTINGS_H
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#define NRF24L01P_SETTINGS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Default configuration parameters
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* @{
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*/
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#define INITIAL_ADDRESS_WIDTH 5
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#define NRF24L01P_MAX_DATA_LENGTH 32
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#ifndef INITIAL_RF_CHANNEL
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#define INITIAL_RF_CHANNEL 5
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#endif
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#define INITIAL_RX_POWER_0dB 0
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/** @} */
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/**
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* @name Timing parameters
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* @{
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*/
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#define DELAY_CS_TOGGLE_US 2
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#define DELAY_AFTER_FUNC_US 2
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#define DELAY_CE_HIGH_US (20)
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#define DELAY_CHANGE_PWR_MODE_US (1500)
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#define DELAY_CHANGE_TXRX_US (130)
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#define DELAY_CE_START_US (5)
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/*
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* This is the time which is needed to physically transmit the data.
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* Compare nrf24l01+ pruduct specification p.42. It is computed just
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* for this setup
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*/
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#define DELAY_DATA_ON_AIR (1300)
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/** @} */
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/**
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* @name Command definitions
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* @{
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*/
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#define CMD_R_REGISTER 0x00
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#define CMD_W_REGISTER 0x20
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#define CMD_R_RX_PAYLOAD 0x61
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#define CMD_W_TX_PAYLOAD 0xa0
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#define CMD_FLUSH_TX 0xe1
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#define CMD_FLUSH_RX 0xe2
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#define CMD_REUSE_TX_PL 0xe3
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#define CMD_R_RX_PL_WID 0x60
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#define CMD_W_ACK_PAYLOAD 0xa8
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#define CMD_W_TX_PAYLOAD_NOACK 0xb0
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#define CMD_NOOP 0xff
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#define REGISTER_MASK 0x1F
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/** @} */
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/**
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* @name Register address definitions
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* @{
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*/
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#define REG_CONFIG 0x00
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#define REG_EN_AA 0x01
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#define REG_EN_RXADDR 0x02
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#define REG_SETUP_AW 0x03
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#define REG_SETUP_RETR 0x04
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#define REG_RF_CH 0x05
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#define REG_RF_SETUP 0x06
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#define REG_STATUS 0x07
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#define REG_OBSERVE_TX 0x08
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#define REG_RPD 0x09
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#define REG_RX_ADDR_P0 0x0a
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#define REG_RX_ADDR_P1 0x0b
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#define REG_RX_ADDR_P2 0x0c
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#define REG_RX_ADDR_P3 0x0d
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#define REG_RX_ADDR_P4 0x0e
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#define REG_RX_ADDR_P5 0x0f
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#define REG_TX_ADDR 0x10
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#define REG_RX_PW_P0 0x11
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#define REG_RX_PW_P1 0x12
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#define REG_RX_PW_P2 0x13
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#define REG_RX_PW_P3 0x14
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#define REG_RX_PW_P4 0x15
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#define REG_RX_PW_P5 0x16
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#define REG_FIFO_STATUS 0x17
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#define REG_DYNPD 0x1c
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#define REG_FEATURE 0x1d
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/** @} */
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/**
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* @name EN_AA register bitmaps
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* @{
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*/
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#define ENAA_P0 0x01
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#define ENAA_P1 0x02
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#define ENAA_P2 0x04
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#define ENAA_P3 0x08
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#define ENAA_P4 0x10
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#define ENAA_P5 0x20
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/** @} */
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/**
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* @name CONFIG register bitmaps
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* @{
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*/
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#define MASK_RX_DR 0x40
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#define MASK_TX_DS 0x20
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#define MASK_MAX_RT 0x10
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#define EN_CRC 0x08
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#define CRCO 0x04
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#define PWR_UP 0x02
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#define PRIM_RX 0x01
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/** @} */
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/**
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* @name STATUS register bitmaps
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* @{
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*/
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#define RX_DR 0x40
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#define TX_DS 0x20
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#define MAX_RT 0x10
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#define RX_P_NO 0x0e
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#define TX_FULL 0x01
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#define ALL_INT_MASK 0x70
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/** @} */
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/**
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* @name RF_SETUP register bitmaps
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* @{
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*/
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#define RF_SETUP_CONT_WAVE (1 << 7)
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#define RF_SETUP_RF_DR_LOW (1 << 5)
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#define RF_SETUP_PLL_LOCK (1 << 4)
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#define RF_SETUP_RF_DR_HIGH (1 << 3)
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#define RF_SETUP_RF_PWR (3 << 1)
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/** @} */
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/**
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* @name Channel mask for the RF_CH register
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*/
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#define RF_CH_MASK 0x7f
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/**
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* @name DYNPD register bitmaps
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* @{
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*/
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#define DYNPD_DPL_P5 (1 << 5)
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#define DYNPD_DPL_P4 (1 << 4)
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#define DYNPD_DPL_P3 (1 << 3)
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#define DYNPD_DPL_P2 (1 << 2)
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#define DYNPD_DPL_P1 (1 << 1)
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#define DYNPD_DPL_P0 (1 << 0)
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/** @} */
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/**
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* @name FEATURE register bitmaps
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* @{
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*/
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#define FEATURE_EN_DPL (1 << 2)
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#define FEATURE_EN_ACK_PAY (1 << 1)
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#define FEATURE_EN_DYN_ACK (1 << 0)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* NRF24L01P_SETTINGS_H */
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/** @} */
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