mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
05f114d0af
- most were trivial
- missing group close or open
- extra space
- no doxygen comment
- name commad might open an implicit group
this hould also be implicit cosed but does not happen somtimes
- crazy: internal declared groups have to be closed internal
76 lines
2.6 KiB
C
76 lines
2.6 KiB
C
/*
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* Copyright (C) 2018 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup drivers_itg320x
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* @brief Register definitions for InvenSense ITG320X 3-axis gyroscope
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* @author Gunar Schorcht <gunar@schorcht.net>
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* @file
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* @{
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*/
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#ifndef ITG320X_REGS_H
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#define ITG320X_REGS_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @name Register addresses
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* @{
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*/
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#define ITG320X_REG_WHO_AM_I (0x00)
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#define ITG320X_REG_SMPLRT_DIV (0x15)
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#define ITG320X_REG_DLPFS (0x16)
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#define ITG320X_REG_INT_CFG (0x17)
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#define ITG320X_REG_INT_STATUS (0x1a)
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#define ITG320X_REG_TEMP_OUT_H (0x1b)
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#define ITG320X_REG_TEMP_OUT_L (0x1c)
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#define ITG320X_REG_GYRO_XOUT_H (0x1d)
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#define ITG320X_REG_GYRO_XOUT_L (0x1e)
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#define ITG320X_REG_GYRO_YOUT_H (0x1f)
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#define ITG320X_REG_GYRO_YOUT_L (0x20)
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#define ITG320X_REG_GYRO_ZOUT_H (0x21)
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#define ITG320X_REG_GYRO_ZOUT_L (0x22)
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#define ITG320X_REG_PWR_MGM (0x3e)
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/** @} */
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/**
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* @name Register structure definitions
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* @{
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*/
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#define ITG320X_REG_DLPFS_FS_SEL (0x18) /**< ITG320X_REG_DLPFS<4:3> */
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#define ITG320X_REG_DLPFS_FS_SEL_VAL (0x18) /**< ITG320X_REG_DLPFS<4:3> = 3 */
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#define ITG320X_REG_DLPFS_DLPF_CFG (0x07) /**< ITG320X_REG_DLPFS<2:0> */
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#define ITG320X_REG_INT_CFG_ACTL (0x80) /**< ITG320X_REG_INT_CFG<7> */
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#define ITG320X_REG_INT_CFG_OPEN (0x40) /**< ITG320X_REG_INT_CFG<6> */
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#define ITG320X_REG_INT_CFG_LATCH_INT (0x20) /**< ITG320X_REG_INT_CFG<5> */
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#define ITG320X_REG_INT_CFG_ANY_RDY_CLR (0x10) /**< ITG320X_REG_INT_CFG<4> */
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#define ITG320X_REG_INT_CFG_ITG_RDY_EN (0x04) /**< ITG320X_REG_INT_CFG<2> */
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#define ITG320X_REG_INT_CFG_RAW_RDY_EN (0x01) /**< ITG320X_REG_INT_CFG<0> */
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#define ITG320X_REG_INT_STATUS_ITG_RDY (0x04) /**< ITG320X_REG_INT_STATUS<2> */
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#define ITG320X_REG_INT_STATUS_RAW_RDY (0x01) /**< ITG320X_REG_INT_STATUS<0> */
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#define ITG320X_REG_PWR_MGM_H_RESET (0x80) /**< ITG320X_REG_PWR_MGM<7> */
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#define ITG320X_REG_PWR_MGM_SLEEP (0x40) /**< ITG320X_REG_PWR_MGM<6> */
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#define ITG320X_REG_PWR_MGM_STBY_XG (0x20) /**< ITG320X_REG_PWR_MGM<5> */
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#define ITG320X_REG_PWR_MGM_STBY_YG (0x10) /**< ITG320X_REG_PWR_MGM<4> */
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#define ITG320X_REG_PWR_MGM_STBY_ZG (0x08) /**< ITG320X_REG_PWR_MGM<3> */
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#define ITG320X_REG_PWR_MGM_CLK_SEL (0x07) /**< ITG320X_REG_PWR_MGM<2:0> */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ITG320X_REGS_H */
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/** @} */
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