mirror of
https://github.com/RIOT-OS/RIOT.git
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05f114d0af
- most were trivial
- missing group close or open
- extra space
- no doxygen comment
- name commad might open an implicit group
this hould also be implicit cosed but does not happen somtimes
- crazy: internal declared groups have to be closed internal
208 lines
5.3 KiB
C
208 lines
5.3 KiB
C
/*
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* Copyright (C) 2015 Ell-i open source co-operative
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* Kaspar Schleiser <kaspar@schleiser.de>
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup drivers_encx24j600
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* @{
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*
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* @file
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* @brief Register definitions for the ENCX24J600 Ethernet device
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*
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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*/
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#ifndef ENCX24J600_DEFINES_H
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#define ENCX24J600_DEFINES_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name SPI instruction set
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* @{
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*/
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#define ENC_RCR 0x00 /* read control register */
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#define ENC_WCR 0x04 /* write control register */
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#define ENC_RCRU 0x20 /* read control register unbanked */
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#define ENC_WCRU 0x22 /* write control register unbanked */
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#define ENC_BFSU 0x24 /* set bits unbanked */
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#define ENC_BFCU 0x26 /* clear bits unbanked */
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#define ENC_RGPDATA 0x28 /* Read EGPDATA */
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#define ENC_WGPDATA 0x2a /* Write EGPDATA */
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#define ENC_RRXDATA 0x2c /* Read ERXDATA */
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#define ENC_WRXDATA 0x2e /* Write ERXDATA */
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#define ENC_RUDADATA 0x30 /* Read EUDADATA */
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#define ENC_WUDADATA 0x32 /* Write EUDADATA */
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#define ENC_BFS 0x80 /* Bit Field Set */
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#define ENC_BFC 0xa0 /* Bit Field Clear */
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#define ENC_SETETHRST 0xca /* System Reset */
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#define ENC_SETPKTDEC 0xcc /* Decrements PKTCNT by setting PKTDEC (ECON1<5>) */
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#define ENC_ENABLERX 0xe8 /* Enables packet reception by setting RXEN (ECON1<0>) */
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#define ENC_DISABLERX 0xea /* Disable packet reception by clearing RXEN (ECON1<0>) */
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#define ENC_SETEIE 0xec /* Enable Ethernet Interrupts by setting INT (ESTAT<16>) */
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#define ENC_CLREIE 0xee /* Disable Ethernet Interrupts by clearing INT (ESTAT<16>) */
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#define ENC_B0SEL 0xc0 /* select bank 0 */
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#define ENC_B1SEL 0xc2 /* select bank 0 */
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#define ENC_B2SEL 0xc4 /* select bank 0 */
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#define ENC_B3SEL 0xc6 /* select bank 0 */
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#define ENC_RBSEL 0xc8 /* Read Bank Select */
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#define ENC_SETTXRTS 0xd4 /* Sets TXRTS (ECON1<1>), sends an Ethernet packet */
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/** @} */
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/**
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* @name 16bit Registers
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* @{
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*/
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#define ENC_ETXST 0x00
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#define ENC_ETXLEN 0x02
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#define ENC_ERXST 0x04
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#define ENC_ERXTAIL 0x06
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#define ENC_ERXHEAD 0x08
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#define ENC_ETXSTAT 0x12
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#define ENC_ETXWIRE 0x14
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#define ENC_EUDAST 0x16
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#define ENC_ESTAT 0x1a
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#define ENC_EIR 0x1c /* Interrupt Flag Register */
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#define ENC_ECON1 0x1e
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#define ENC_ERXFCON 0x34 /* Receive filter control register */
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#define ENC_MACON2 0x42
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#define ENC_MAMXFL 0x4a /* MAC maximum frame length */
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#define ENC_MAADR3 0x60 /* MAC address byte 5&6 */
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#define ENC_MAADR2 0x62 /* MAC address byte 3&4 */
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#define ENC_MAADR1 0x64 /* MAC address byte 1&2 */
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#define ENC_MIWR 0x66
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#define ENC_MIREGADR 0x54
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#define ENC_ECON2 0x6e
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#define ENC_EIE 0x72 /* Interrupt Enable Register */
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#define ENC_EGPRDPT 0x86 /* General Purpose SRAM read pointer */
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#define ENC_EGPWRPT 0x88 /* General Purpose SRAM write pointer */
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#define ENC_ERXRDPT 0x8a /* RX buffer read pointer */
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#define ENC_ERXWRPT 0x8c /* RX buffer write pointer */
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/** @} */
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/**
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* @name PHY Registers
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*
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* (access with phy_reg_* functions)
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*
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* @{
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*/
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#define ENC_PHCON1 0x00
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#define ENC_PHSTAT1 0x01
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#define ENC_PHANA 0x04
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#define ENC_PHANLPA 0x05
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#define ENC_PHANE 0x06
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#define ENC_PHCON2 0x11
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#define ENC_PHSTAT2 0x1b
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#define ENC_PHSTAT3 0x1f
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/** @} */
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/**
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* @name ESTAT bits
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* @{
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*/
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#define ENC_PHYLNK (1<<8)
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#define ENC_CLKRDY (1<<12)
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/** @} */
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/**
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* @name ECON1 bits
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* @{
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*/
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#define ENC_RXEN (1<<0)
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#define ENC_TXRTS (1<<1)
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#define ENC_DMANOCS (1<<2)
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#define ENC_DMACSSD (1<<3)
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#define ENC_DMACPY (1<<4)
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#define ENC_DMAST (1<<5)
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#define ENC_FCOP0 (1<<6)
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#define ENC_FCOP1 (1<<7)
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#define ENC_PKTDEC (1<<8)
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#define ENC_AESOP0 (1<<9)
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#define ENC_AESOP1 (1<<10)
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#define ENC_AESST (1<<11)
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#define ENC_HASHLST (1<<12)
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#define ENC_HASHOP (1<<13)
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#define ENC_HASHEN (1<<14)
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#define ENC_MODEXST (1<<15)
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/** @} */
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/**
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* @name ECON2 bits
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* @{
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*/
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#define ENC_ETHRST (1<<4)
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#define ENC_AUTOFC (1<<7) /* automatic flow control enable bit */
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/** @} */
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/**
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* @name EIR bits
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* @{
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*/
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#define ENC_PCFULIE (1<<0)
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#define ENC_RXABTIE (1<<1)
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#define ENC_TXABTIE (1<<2)
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#define ENC_TXIE (1<<3)
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#define ENC_DMAIE (1<<5)
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#define ENC_PKTIE (1<<6)
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#define ENC_LINKIE (1<<11)
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#define ENC_AESIE (1<<12)
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#define ENC_HASHIE (1<<13)
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#define ENC_MODEXIE (1<<14)
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#define ENC_INTIE (1<<15)
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/** @} */
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/**
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* @name EIR bits
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* @{
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*/
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#define ENC_PCFULIF (1<<0)
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#define ENC_RXABTIF (1<<1)
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#define ENC_TXABTIF (1<<2)
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#define ENC_TXIF (1<<3)
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#define ENC_DMAIF (1<<5)
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#define ENC_PKTIF (1<<6)
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#define ENC_LINKIF (1<<11)
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#define ENC_AESIF (1<<12)
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#define ENC_HASHIF (1<<13)
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#define ENC_MODEXIF (1<<14)
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#define ENC_CRYPTEN (1<<15)
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/** @} */
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/**
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* @brief ERXFCON bits
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* @{
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*/
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#define ENC_MCEN (1<<1)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* ENCX24J600_DEFINES_H */
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/** @} */
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