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331 lines
12 KiB
C
331 lines
12 KiB
C
/*
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* Copyright (C) 2018 Otto-von-Guericke-Universität Magdeburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup drivers_cc110x
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* @{
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*
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* @file
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* @brief On-chip settings for the TI CC1100/CC1101 transceiver
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*
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* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
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* @}
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*/
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#include "cc110x.h"
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#include "cc110x_internal.h"
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const uint8_t cc110x_conf[CC110X_CONF_SIZE] = {
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/*
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* IOCFG2; default: 0x29 (CHIP_RDYn)
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* Invert GDO2: off,
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* GDO2: Go high when RX data should be read
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*
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* Why not default?
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* GDO2 will be used to be notified about FIFO events (e.g. refilling TX
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* FIFO is needed during transmission, reading from RX FIFO is needed
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* during reception)
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*/
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CC110X_GDO_ON_RX_DATA,
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/*
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* IOCFG1; default: 0x2E (3-state)
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* Invert GDO1: off,
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* GDO1: 3-state (required when SPI interface is shared with other devices)
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*/
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0x2E,
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/*
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* IOCFG0; default: 0x3F (CLK_XOSC/192)
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* Invert GDO0: off,
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* GDO0: Go high on PLL in lock
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*
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* Why not default?
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* GDO0 will be used to be notified when a packet is coming while in RX
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* mode (will go high during transmission) and when sending is completed
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* while in TX (remains high during transmission and will go back low when
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* done).
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*/
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CC110X_GDO_ON_TRANSMISSION,
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/*
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* FIFOTHR; default: 0x07
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* TEST1 = 0x31 and TEST2 = 0x88 when waking up from SLEEP,
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* 0dB RX attenuation,
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* threshold for FIFOs: TX FIFO = 33, RX FIFO = 32
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*/
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0x07,
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/*
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* SYNC1, SYNC0; defaults: 0xD3, 0x91
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* Use 0xD3,0x91 as sync word
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*/
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0xD3, /*< SYNC1 */
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0x91, /*< SYNC0 */
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/*
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* PKTLEN; default: 0xFF
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* Packet length in bytes in fixed length mode, else maximum length
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*/
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0xff,
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/*
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* PKTCTRL1; default: 0x04
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* PQT: Accept all sync words, regardless of preamble quality
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* CRC_AUTOFLUSH: Do not auto-flush RX FIFO on incorrect CRC
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* APPEND_STATUS: Do not add 2 bytes of status information in RX FIFO
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* ADDR_CHK: Filter incoming frames in hardware by address: Only frames
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* with destination address 0x00 (broadcast) or with with the
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* layer-2 address of the transceiver are accepted.
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*
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* Why not default?
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* - The RSSI, LQI and CRC info are also available via status registers.
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* Thus, it is not worth to sacrifice two bytes of RX FIFO for it.
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* - Hardware address filtering could reduce the number IRQs generated
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* (e.g. a huge frame is dropped before it fully received) which reduces
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* the system's load. Thus, it is enabled.
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*/
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CC110X_PKTCTRL1_VALUE | CC110X_PKTCTRL1_ADDR_MATCH,
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/*
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* PKTCTRL0; default: 0x45
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* Data whitening enabled, use RX/TX FIFOs, CRC enabled,
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* variable packet length
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*/
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0x45,
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/*
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* ADDR; default: 0x00
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* Address will overwritten later
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*
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* Why not default?
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* 0x00 is used as broadcast address. Using it would increase chance to
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* receive message during device initialization and thus power consumption.
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*/
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0xFF,
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/*
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* CHANNR; default: 0x00
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* Channel number 0 by default
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*/
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0x00,
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/*
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* FSCTRL1; default: 0x0C
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* Intermediate frequency: 0x0C * 26MHz / 1024 = 304.7kHz
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*
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* Why not defaults?
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* See MDMCFG4, MDMCFG3
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*/
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0x0C,
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/*
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* FSCTRL0; default: 0x00
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* Frequency offset to base frequency: 0kHz
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*/
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0x00,
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/*
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* FREQ2, FREQ1, FREQ0; defaults: 0x1E, 0xC4, 0xEC
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* 0x2146E4 * 26MHz / 65536 = 865.1998 MHz (LoRa Channel 10)
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*
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* Why not defaults?
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* Default is 800.000 MHz, which is not in a license free frequency band.
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* Using LoRa channel 10 instead.
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*/
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0x21, /*< FREQ2 */
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0x46, /*< FREQ1 */
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0xE4, /*< FREQ0 */
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/*
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* MDMCFG4, MDMCFG3; defaults: 0x8C, 0x22
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* 541.67 kHz channel filter bandwidth,
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* 249.94 kBaud symbol rate
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*
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* Why not defaults?
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* Using 250 kBaud (==> 250kBit/s when 2-FSK/GFSK/ASK) to compete with
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* 802.15.4 in data rate.
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* Using settings listed in Table 7 (pages 12ff in the data sheet):
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* - 250 kBaud
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* - GFSK modulation
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* - 304 kHz IF frequency
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* - 540 kHz channel filter bandwidth
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* - 127 kHz deviation
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*/
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0x2D, /*< MDMCFG4 */
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0x3B, /*< MDMCFG3 */
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/*
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* MDMCFG2; default: 0x02
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* DC blocking filter on,
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* GFSK modulation,
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* no manchester code,
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* Enable RX when 30 bits of the 32 bits sync word are received correctly
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*
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* Why not default?
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* Default expects all 16 bits of a two byte sync word to be correctly
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* received. The data sheet recommends to expect 30 bits of a four byte
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* sync word to be correctly received instead (see section 15 on page 37),
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* so we go for this.
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*
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* Using GFSK instead of 2-FSK reduces the modulated spectrum width and is
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* suggested in Table 7 of the datasheet, see MDMCFG4, MDMCFG3
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*/
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0x13,
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/*
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* MDMCFG1, MDMCFG0; defaults: 0x22, 0xF8
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* FEC disabled,
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* 4 preamble bytes,
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* 49.99 kHz distance between channel centre frequencies (closest to 50kHz)
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*
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* Why not defaults?
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* This driver uses an translation layer between physical channels (with
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* 50 kHz distance) and "virtual" channel numbers as seen outside of the
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* driver. This allows to set the frequency in a range of 12.75 MHz with
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* a resolution of 50kHz - this seems to allow to configure all desired
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* channel layouts.
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*/
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0x20, /*< MDMCFG1 */
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0xF8, /*< MDMCFG0 */
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/*
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* DEVIATN; default: 0x47
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* Deviation of frequency to encode data: +- 126.953kHz in 2-FSK/4-FSK/GFSK
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*
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* Why not default?
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* Higher deviation required for reliable operation at 250 kbps data rate.
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*/
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0x62,
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/*
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* MCSM2; default: 0x07
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* No direct RX termination on RSSI measurement (only for ASK/OOK),
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* on RX timeout check for sync word and ignore PQI,
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* no RX timeout
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*/
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0x07,
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/*
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* MCSM1; default: 0x30
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* CCA: Enter TX even when channel is detected busy
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* go to idle after packet received,
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* go to idle after packet sent
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*
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* Why not default?
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* By default the transceiver refuses to enter TX when the channel is
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* detected busy. While this is desired, checking if TX was successfully
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* entered is too slow and generated interrupts on the GDO2 pin are easily
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* missed. However, reading the carrier sense value in the PKTSTATUS
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* registers allows to implement this feature in software in a faster
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* way. In addition to not missing GDO2 interrupts, this allows the send
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* function to give feedback right away when the channel is busy.
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*/
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0x00,
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/*
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* MCSM0; default: 0x04
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* Auto calibration: Disabled, driver has to manage
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* delay to allow supply voltage to stabilize: 149-155 microseconds
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* pin radio control option is off,
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* oscillator is off in sleep state
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*
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* Why not default?
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* Using 149µs-155µs instead of the default 37µs-39µs as PO_TIMEOUT is
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* encouraged by the data sheet for robust operation
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*/
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0x08,
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/*
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* FOCCFG; default: 0x36
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* Freeze frequency offset compensation etc until CS high: yes
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* frequency compensation loop gain before sync word: 3K
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* frequency compensation loop gain after sync word: K/2
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* saturation point for frequency offset compensation: 25% channel bandwidth
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* (incompatible with ASK/OOK)
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*/
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0x36,
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/*
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* BSCFG; default: 0x6C
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* Clock recovery feedback loop integral gain before sync word: 2K_i,
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* clock recovery feedback loop proportional gain before sync word: 3K_p,
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* clock recovery feedback loop integral gain after sync word: K_i/2
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* clock recovery feedback loop proportional gain after sync word: K_p,
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* data rate offset compensation: Disabled
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*/
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0x6C,
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/*
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* AGCCTRL2; default: 0x03
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* Maximum allowable DVGA gain: No limitation, maximum DVGA gain can be used
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* Maximum allowable LNA + LNA2 gain: No limitation
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* target amplitude from channel filter: 33 dB (default)
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*/
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0x03,
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/*
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* AGCCTRL1; default: 0x40
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* LNA priority: Decrease LNA gain first, start decreasing LNA2 gain when
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* LNA gain reached minimum
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* Relative carrier sense threshold: Disabled
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* Absolute carrier sense threshold: At MAGN_TARGET
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*/
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0x40,
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/*
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* AGCCTRL0; default: 0x91
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* HYST_LEVEL: Medium hysteresis, medium asymmetric dead zone, medium gain
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* Adjust gain after how many channel filter samples: After 16 samples
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* Freeze AGC gain: Never; perform gain adjustments as required
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* FILTER_LENGTH:
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* - 16 channel filter samples when 2-FSK, 4-FSK, or MSK is used
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* - 8 dB decision baundry when OOK/ASK is used
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*/
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0x91,
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/*
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* WOREVT1, WOREVT0, WORCTRL; defaults: 0x87, 0x6B, 0xF8
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* Event0 Timeout: 1.000 seconds
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* RC_PD: 1 (The datasheet is quite cryptic regarding this setting)
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* Event1 Timeout: 1.333ms - 1.385ms (depending on crystal frequency)
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* RC oscillator calibration: Enabled
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* WOR_RES: 0 (Relevant for Event0 resolution and maximum timeout)
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*/
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0x87, /*< WOREVT1 */
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0x6B, /*< WOREVT0 */
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0xF8, /*< WORCTRL */
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/*
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* FREND1; default: 0x56
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* LNA_CURRENT: 0b01
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* LNA2MIX_CURRENT: 0b01
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* LODIV_BUF_CURRENT_RW: 0b01
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* MIX_CURRENT: 0b10
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*/
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0x56,
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/*
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* FREND0; default: 0x10
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* LODIV_BUF_CURRENT_TX: 0b01
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* Index in PA_POWER table (in 0..7, default is 0): 4 (0dBm)
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*
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* Why not default:
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* Use a reasonable TX power level instead of the lowest.
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*/
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0x10 | CC110X_TX_POWER_0_DBM,
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/*
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* FSCAL3, FSCAL2, FSCAL1, FSCAL0; defaults: 0xA9, 0x0A, 0x20, 0x0d
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* These values store calibration date of the CC1100/CC1101 transceiver.
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* Once the transceiver performs a calibration, those registers are updated
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* with the new calibration data. In a "stable" environment (e.g. constant
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* channel/frequency, stable humidity, temperature, supply voltage etc.)
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* the obtained values could be written to the transceiver and calibration
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* could be turned off completely.
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*
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* Fast channel hopping could be performed by obtaining the FSCAL1
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* calibration data for each channel and storing it in the MCU's RAM.
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* The other calibration values is frequency independent according to the
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* data sheet, but depends on temperature etc.
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*
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* Once the FSCAL1 values for each channel are stored, the calibration can
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* be disabled and the stored FSCAL1 data can be uploaded for each channel
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* hop. A re-calibration from time to time is suggested to cope with changes
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* in the environment, e.g. in temperature or supply voltage.
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*
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* Why not defaults?
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* Using "magic" values obtained with SmartRF Studio software for 868 MHz
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* band.
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*/
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0xEA, /*< FSCAL3: charge pump current calibration, frequency independent */
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0x2A, /*< FSCAL2: VCO current calibration, frequency independent */
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0x00, /*< FSCAL1: VCO capacitance calibration, frequency dependent */
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0x1F, /*< FSCAL0: "Magic number", use SmartRF Studio to obtain */
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/*
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* RCCTRL1, RCCTRL0; defaults: 0x41, 0x00
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* RC oscillator configuration, no explanation given in data sheet.
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*/
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0x41, /*< RCCTRL1 */
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0x00, /*< RCCTRL0 */
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};
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const uint8_t cc110x_magic_registers[3] = { 0x88, 0x31, 0x09 };
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