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76 lines
1.5 KiB
C
76 lines
1.5 KiB
C
/*
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* Copyright (C) 2022 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_esp_common
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* @{
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*
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* @file
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* @brief Exception handling for RISC-V-based ESP SoCs
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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* @}
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*/
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#include <inttypes.h>
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#include "kernel_defines.h"
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#include "panic.h"
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#include "periph/pm.h"
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#include "esp_attr.h"
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#include "riscv/rvruntime-frames.h"
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#include "rom/ets_sys.h"
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static const char *exceptions[] = {
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"nil",
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"0x1: PMP Instruction access fault",
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"0x2: Illegal Instruction",
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"0x3: Hardware Breakpoint/Watchpoint or EBREAK",
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"nil",
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"0x5: PMP Load access fault",
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"nil",
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"0x7: PMP Store access fault",
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"0x8: ECALL from U mode",
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"nil",
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"nil",
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"0xb: ECALL from M mode",
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};
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static RvExcFrame *_frame = NULL;
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void init_exceptions (void)
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{
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}
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void IRAM_ATTR xt_unhandled_exception(RvExcFrame *frame)
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{
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_frame = frame;
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core_panic(PANIC_GENERAL_ERROR, "Unhandled exception");
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}
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void IRAM_ATTR panicHandler(RvExcFrame *frame)
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{
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_frame = frame;
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core_panic(PANIC_GENERAL_ERROR, "Panic handler");
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}
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extern void heap_stats(void);
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void panic_arch(void)
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{
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if (_frame) {
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/* TODO */
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ets_printf("Exception @0x%08"PRIx32", cause %s\n",
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_frame->mepc, exceptions[_frame->mcause]);
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}
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#if defined(DEVELHELP)
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heap_stats();
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#endif
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}
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