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212 lines
8.4 KiB
C
212 lines
8.4 KiB
C
/** esp/uart.h
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*
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* Configuration of UART registers.
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*
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* Part of esp-open-rtos
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* Copyright (C) 2015 Superhouse Automation Pty Ltd
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* BSD Licensed as described in the file LICENSE
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*/
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/*
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Copyright (c) 2015, SuperHouse Automation Pty Ltd
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef UART_REGS_H
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#define UART_REGS_H
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#ifndef DOXYGEN
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#include "esp/types.h"
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#include "common_macros.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Register definitions for the UART peripherals on the ESP8266.
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*
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* There are twp UART devices built into the ESP8266:
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* UART(0) is at 0x60000000
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* UART(1) is at 0x60000F00
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*
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* Each device is allocated a block of 64 32-bit registers (256 bytes of
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* address space) to communicate with application code.
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*/
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#define UART_BASE 0x60000000
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#define UART(i) (*(struct UART_REGS *)(UART_BASE + (i)*0xf00))
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#define UART0_BASE UART_BASE
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#define UART1_BASE (UART_BASE + 0xf00)
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struct UART_REGS {
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uint32_t volatile FIFO; // 0x00
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uint32_t volatile INT_RAW; // 0x04
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uint32_t volatile INT_STATUS; // 0x08
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uint32_t volatile INT_ENABLE; // 0x0c
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uint32_t volatile INT_CLEAR; // 0x10
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uint32_t volatile CLOCK_DIVIDER; // 0x14
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uint32_t volatile AUTOBAUD; // 0x18
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uint32_t volatile STATUS; // 0x1c
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uint32_t volatile CONF0; // 0x20
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uint32_t volatile CONF1; // 0x24
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uint32_t volatile LOW_PULSE; // 0x28
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uint32_t volatile HIGH_PULSE; // 0x2c
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uint32_t volatile PULSE_COUNT; // 0x30
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uint32_t volatile _unused[17]; // 0x34 - 0x74
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uint32_t volatile DATE; // 0x78
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uint32_t volatile ID; // 0x7c
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};
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_Static_assert(sizeof(struct UART_REGS) == 0x80, "UART_REGS is the wrong size");
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/* Details for FIFO register */
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#define UART_FIFO_DATA_M 0x000000ff
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#define UART_FIFO_DATA_S 0
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/* Details for INT_RAW register */
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#define UART_INT_RAW_RXFIFO_TIMEOUT BIT(8)
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#define UART_INT_RAW_BREAK_DETECTED BIT(7)
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#define UART_INT_RAW_CTS_CHANGED BIT(6)
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#define UART_INT_RAW_DSR_CHANGED BIT(5)
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#define UART_INT_RAW_RXFIFO_OVERFLOW BIT(4)
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#define UART_INT_RAW_FRAMING_ERR BIT(3)
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#define UART_INT_RAW_PARITY_ERR BIT(2)
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#define UART_INT_RAW_TXFIFO_EMPTY BIT(1)
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#define UART_INT_RAW_RXFIFO_FULL BIT(0)
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/* Details for INT_STATUS register */
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#define UART_INT_STATUS_RXFIFO_TIMEOUT BIT(8)
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#define UART_INT_STATUS_BREAK_DETECTED BIT(7)
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#define UART_INT_STATUS_CTS_CHANGED BIT(6)
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#define UART_INT_STATUS_DSR_CHANGED BIT(5)
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#define UART_INT_STATUS_RXFIFO_OVERFLOW BIT(4)
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#define UART_INT_STATUS_FRAMING_ERR BIT(3)
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#define UART_INT_STATUS_PARITY_ERR BIT(2)
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#define UART_INT_STATUS_TXFIFO_EMPTY BIT(1)
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#define UART_INT_STATUS_RXFIFO_FULL BIT(0)
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/* Details for INT_ENABLE register */
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#define UART_INT_ENABLE_RXFIFO_TIMEOUT BIT(8)
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#define UART_INT_ENABLE_BREAK_DETECTED BIT(7)
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#define UART_INT_ENABLE_CTS_CHANGED BIT(6)
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#define UART_INT_ENABLE_DSR_CHANGED BIT(5)
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#define UART_INT_ENABLE_RXFIFO_OVERFLOW BIT(4)
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#define UART_INT_ENABLE_FRAMING_ERR BIT(3)
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#define UART_INT_ENABLE_PARITY_ERR BIT(2)
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#define UART_INT_ENABLE_TXFIFO_EMPTY BIT(1)
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#define UART_INT_ENABLE_RXFIFO_FULL BIT(0)
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/* Details for INT_CLEAR register */
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#define UART_INT_CLEAR_RXFIFO_TIMEOUT BIT(8)
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#define UART_INT_CLEAR_BREAK_DETECTED BIT(7)
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#define UART_INT_CLEAR_CTS_CHANGED BIT(6)
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#define UART_INT_CLEAR_DSR_CHANGED BIT(5)
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#define UART_INT_CLEAR_RXFIFO_OVERFLOW BIT(4)
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#define UART_INT_CLEAR_FRAMING_ERR BIT(3)
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#define UART_INT_CLEAR_PARITY_ERR BIT(2)
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#define UART_INT_CLEAR_TXFIFO_EMPTY BIT(1)
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#define UART_INT_CLEAR_RXFIFO_FULL BIT(0)
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/* Details for CLOCK_DIVIDER register */
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#define UART_CLOCK_DIVIDER_VALUE_M 0x000fffff
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#define UART_CLOCK_DIVIDER_VALUE_S 0
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/* Details for AUTOBAUD register */
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#define UART_AUTOBAUD_GLITCH_FILTER_M 0x000000FF
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#define UART_AUTOBAUD_GLITCH_FILTER_S 8
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#define UART_AUTOBAUD_ENABLE BIT(0)
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/* Details for STATUS register */
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#define UART_STATUS_TXD BIT(31)
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#define UART_STATUS_RTS BIT(30)
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#define UART_STATUS_DTR BIT(29)
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#define UART_STATUS_TXFIFO_COUNT_M 0x000000ff
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#define UART_STATUS_TXFIFO_COUNT_S 16
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#define UART_STATUS_RXD BIT(15)
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#define UART_STATUS_CTS BIT(14)
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#define UART_STATUS_DSR BIT(13)
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#define UART_STATUS_RXFIFO_COUNT_M 0x000000ff
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#define UART_STATUS_RXFIFO_COUNT_S 0
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/* Details for CONF0 register */
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#define UART_CONF0_DTR_INVERTED BIT(24)
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#define UART_CONF0_RTS_INVERTED BIT(23)
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#define UART_CONF0_TXD_INVERTED BIT(22)
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#define UART_CONF0_DSR_INVERTED BIT(21)
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#define UART_CONF0_CTS_INVERTED BIT(20)
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#define UART_CONF0_RXD_INVERTED BIT(19)
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#define UART_CONF0_TXFIFO_RESET BIT(18)
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#define UART_CONF0_RXFIFO_RESET BIT(17)
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#define UART_CONF0_IRDA_ENABLE BIT(16)
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#define UART_CONF0_TX_FLOW_ENABLE BIT(15)
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#define UART_CONF0_LOOPBACK BIT(14)
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#define UART_CONF0_IRDA_RX_INVERTED BIT(13)
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#define UART_CONF0_IRDA_TX_INVERTED BIT(12)
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#define UART_CONF0_IRDA_WCTL BIT(11)
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#define UART_CONF0_IRDA_TX_ENABLE BIT(10)
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#define UART_CONF0_IRDA_DUPLEX BIT(9)
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#define UART_CONF0_TXD_BREAK BIT(8)
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#define UART_CONF0_SW_DTR BIT(7)
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#define UART_CONF0_SW_RTS BIT(6)
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#define UART_CONF0_STOP_BITS_M 0x00000003
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#define UART_CONF0_STOP_BITS_S 4
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#define UART_CONF0_BYTE_LEN_M 0x00000003
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#define UART_CONF0_BYTE_LEN_S 2
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#define UART_CONF0_PARITY_ENABLE BIT(1)
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#define UART_CONF0_PARITY BIT(0) //FIXME: does this indicate odd or even?
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/* Details for CONF1 register */
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#define UART_CONF1_RX_TIMEOUT_ENABLE BIT(31)
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#define UART_CONF1_RX_TIMEOUT_THRESHOLD_M 0x0000007f
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#define UART_CONF1_RX_TIMEOUT_THRESHOLD_S 24
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#define UART_CONF1_RX_FLOWCTRL_ENABLE BIT(23)
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#define UART_CONF1_RX_FLOWCTRL_THRESHOLD_M 0x0000007f
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#define UART_CONF1_RX_FLOWCTRL_THRESHOLD_S 16
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#define UART_CONF1_TXFIFO_EMPTY_THRESHOLD_M 0x0000007f
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#define UART_CONF1_TXFIFO_EMPTY_THRESHOLD_S 8
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#define UART_CONF1_RXFIFO_FULL_THRESHOLD_M 0x0000007f
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#define UART_CONF1_RXFIFO_FULL_THRESHOLD_S 0
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/* Details for LOW_PULSE register */
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#define UART_LOW_PULSE_MIN_M 0x000fffff
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#define UART_LOW_PULSE_MIN_S 0
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/* Details for HIGH_PULSE register */
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#define UART_HIGH_PULSE_MIN_M 0x000fffff
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#define UART_HIGH_PULSE_MIN_S 0
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/* Details for PULSE_COUNT register */
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#define UART_PULSE_COUNT_VALUE_M 0x000003ff
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#define UART_PULSE_COUNT_VALUE_S 0
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#ifdef __cplusplus
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}
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#endif
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#endif // DOXYGEN
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#endif /* UART_REGS_H */
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