mirror of
https://github.com/RIOT-OS/RIOT.git
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286 lines
7.9 KiB
C
286 lines
7.9 KiB
C
/*
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* Copyright (C) 2016 OTA keys S.A.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-f207
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the nucleo-f207 board
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*
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* @author Vincent Dupont <vincent@otakeys.com>
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* @author Aurelien Gonce <aurelien.gonce@altran.fr>
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* @author Toon Stegen <toon.stegen@altran.com>
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*/
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#ifndef PERIPH_CONF_H_
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#define PERIPH_CONF_H_
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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#define CLOCK_HSE (8000000U) /* external oscillator */
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#define CLOCK_CORECLOCK (120000000U) /* desired core clock frequency */
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/* the actual PLL values are automatically generated */
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#define CLOCK_PLL_M (CLOCK_HSE / 1000000)
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#define CLOCK_PLL_N ((CLOCK_CORECLOCK / 1000000) * 2)
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#define CLOCK_PLL_P (2U)
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#define CLOCK_PLL_Q (CLOCK_PLL_N / 48)
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_5WS
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/* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
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* @brief PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.dev = TIM3,
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.rcc_mask = RCC_APB1ENR_TIM3EN,
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.pins = { GPIO_PIN(PORT_C, 6), GPIO_PIN(PORT_C, 7),
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GPIO_PIN(PORT_C, 8), GPIO_PIN(PORT_C, 9) },
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.af = GPIO_AF2,
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.chan = 4,
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.bus = APB1
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}
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};
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#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
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/** @} */
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/**
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* @brief Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM2,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.bus = APB1,
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.irqn = TIM2_IRQn
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},
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{
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.dev = TIM5,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM5EN,
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.bus = APB1,
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.irqn = TIM5_IRQn
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},
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{
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.dev = TIM4,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM4EN,
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.bus = APB1,
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.irqn = TIM4_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim2
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#define TIMER_1_ISR isr_tim5
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#define TIMER_2_ISR isr_tim3
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#define TIMER_3_ISR isr_tim4
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @brief UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART3,
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.rcc_mask = RCC_APB1ENR_USART3EN,
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.rx_pin = GPIO_PIN(PORT_D, 9),
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.tx_pin = GPIO_PIN(PORT_D, 8),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART3_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 3,
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.dma_chan = 4
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#endif
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},
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_D, 6),
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.tx_pin = GPIO_PIN(PORT_D, 5),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 6,
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.dma_chan = 4
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#endif
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},
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_A, 10),
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.tx_pin = GPIO_PIN(PORT_A, 9),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB2,
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.irqn = USART1_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 7,
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.dma_chan = 4
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#endif
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}
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};
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#define UART_0_ISR (isr_usart3)
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#define UART_0_DMA_ISR (isr_dma1_stream3)
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#define UART_1_ISR (isr_usart2)
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#define UART_1_DMA_ISR (isr_dma1_stream6)
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#define UART_2_ISR (isr_usart1)
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#define UART_2_DMA_ISR (isr_dma1_stream7)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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#define SPI_NUMOF (2U)
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#define SPI_0_EN 1
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#define SPI_1_EN 1
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#define SPI_IRQ_PRIO 1
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/* SPI 0 device config */
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#define SPI_0_DEV SPI1
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#define SPI_0_CLKEN() (periph_clk_en(APB2, RCC_APB2ENR_SPI1EN))
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#define SPI_0_CLKDIS() (periph_clk_dis(APB2, RCC_APB2ENR_SPI1EN))
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#define SPI_0_BUS_DIV 1 /* 1 -> SPI bus runs with half CPU clock, 0 -> quarter CPU clock */
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#define SPI_0_IRQ SPI1_IRQn
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#define SPI_0_IRQ_HANDLER isr_spi1
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/* SPI 0 pin configuration */
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#define SPI_0_SCK_PORT GPIOA /* A5 pin is shared with the green LED. */
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#define SPI_0_SCK_PIN 5
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#define SPI_0_SCK_AF 5
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#define SPI_0_SCK_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
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#define SPI_0_MISO_PORT GPIOA
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#define SPI_0_MISO_PIN 6
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#define SPI_0_MISO_AF 5
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#define SPI_0_MISO_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
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#define SPI_0_MOSI_PORT GPIOA
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#define SPI_0_MOSI_PIN 7
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#define SPI_0_MOSI_AF 5
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#define SPI_0_MOSI_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOAEN))
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/* SPI 1 device config */
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#define SPI_1_DEV SPI2
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#define SPI_1_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_SPI2EN))
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#define SPI_1_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_SPI2EN))
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#define SPI_1_BUS_DIV 0 /* 1 -> SPI bus runs with half CPU clock, 0 -> quarter CPU clock */
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#define SPI_1_IRQ SPI2_IRQn
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#define SPI_1_IRQ_HANDLER isr_spi2
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/* SPI 1 pin configuration */
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#define SPI_1_SCK_PORT GPIOB
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#define SPI_1_SCK_PIN 3
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#define SPI_1_SCK_AF 5
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#define SPI_1_SCK_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
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#define SPI_1_MISO_PORT GPIOB
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#define SPI_1_MISO_PIN 4
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#define SPI_1_MISO_AF 5
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#define SPI_1_MISO_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
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#define SPI_1_MOSI_PORT GPIOB
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#define SPI_1_MOSI_PIN 5
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#define SPI_1_MOSI_AF 5
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#define SPI_1_MOSI_PORT_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (1U)
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#define I2C_0_EN 1
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#define I2C_IRQ_PRIO 1
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#define I2C_APBCLK (CLOCK_APB1)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C1
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#define I2C_0_CLKEN() (periph_clk_en(APB1, RCC_APB1ENR_I2C1EN))
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#define I2C_0_CLKDIS() (periph_clk_dis(APB1, RCC_APB1ENR_I2C1EN))
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#define I2C_0_EVT_IRQ I2C1_EV_IRQn
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#define I2C_0_EVT_ISR isr_i2c1_ev
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#define I2C_0_ERR_IRQ I2C1_ER_IRQn
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#define I2C_0_ERR_ISR isr_i2c1_er
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/* I2C 0 pin configuration */
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#define I2C_0_SCL_PORT GPIOB
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#define I2C_0_SCL_PIN 8
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#define I2C_0_SCL_AF 4
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#define I2C_0_SCL_PULLUP 0
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#define I2C_0_SCL_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
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#define I2C_0_SDA_PORT GPIOB
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#define I2C_0_SDA_PIN 9
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#define I2C_0_SDA_AF 4
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#define I2C_0_SDA_PULLUP 0
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#define I2C_0_SDA_CLKEN() (periph_clk_en(AHB1, RCC_AHB1ENR_GPIOBEN))
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/** @} */
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/**
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* @brief ADC configuration
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*
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* We need to define the following fields:
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* PIN, device (ADCx), channel
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* @{
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*/
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#define ADC_CONFIG { \
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{GPIO_PIN(PORT_A, 4), 0, 0}, \
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{GPIO_PIN(PORT_A, 5), 1, 0} \
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}
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#define ADC_NUMOF (2)
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/** @} */
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/**
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* @brief DAC configuration
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* @{
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*/
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#define DAC_NUMOF (0)
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/** @} */
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/**
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* @brief RTC configuration
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* @{
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*/
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#define RTC_NUMOF (1)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H_ */
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/** @} */
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