mirror of
https://github.com/RIOT-OS/RIOT.git
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7749e621b8
Casting pointers to volatile memory to pointers to regular memory is permitted, but using those pointers to access the memory results in undefined behavior. This commit changes the casts to no longer drop the volatile qualifier. References: https://en.cppreference.com/w/c/language/volatile
372 lines
15 KiB
C
372 lines
15 KiB
C
/*
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* Copyright (C) 2015-2016 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup core_util
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* @{
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*
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* @file
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*
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* @brief Implementation of C11 atomic operations if GCC does not provide an
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* implementation.
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*
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* GCC with -mcpu=cortex-m3 and cortex-m4 generate LDREX/STREX instructions
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* instead of library calls. There is however currently (2015-05-29) no
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* implementation for Cortex-M0, since it lacks the lock-free atomic operations
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* found in the M3 and M4 cores.
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*
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* @note Other CPUs (e.g. msp430, avr) might need this too, but current MSP430
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* GCC in Ubuntu/Debian is stuck at version 4.6 which does not provide C11
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* language support which makes it difficult to actually make use of this on
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* that platform.
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*
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* @note This implementation completely ignores the memory model parameter
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*
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* @see https://gcc.gnu.org/wiki/Atomic/GCCMM/LIbrary
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* @see https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#include <stddef.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdatomic.h>
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#include <string.h>
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#include "irq.h"
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/* GCC documentation refers to the types as I1, I2, I4, I8, I16 */
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typedef uint8_t I1;
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typedef uint16_t I2;
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/* the builtins are declared with "unsigned int", but "uint32_t" is typedef'ed
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* to "long unsigned int" on most platforms where "sizeof(int) == 4. */
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#if __SIZEOF_INT__ == 4
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typedef unsigned int I4;
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#else
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typedef uint32_t I4;
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#endif
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typedef uint64_t I8;
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/* typedef __uint128_t I16; */ /* No 128 bit integer support yet */
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/**
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* @brief This is a macro that defines a function named __atomic_load_<em>n</em>
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*
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* @param[in] n width of the data, in bytes
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*/
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#define TEMPLATE_ATOMIC_LOAD_N(n) \
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I##n __atomic_load_##n (const volatile void *ptr, int memorder) \
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{ \
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(void) memorder; \
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unsigned int mask = irq_disable(); \
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I##n old = *(const volatile I##n *)ptr; \
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irq_restore(mask); \
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return old; \
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}
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/**
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* @brief This is a macro that defines a function named __atomic_store_<em>n</em>
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*
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* @param[in] n width of the data, in bytes
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*/
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#define TEMPLATE_ATOMIC_STORE_N(n) \
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void __atomic_store_##n (volatile void *ptr, I##n val, int memorder) \
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{ \
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(void) memorder; \
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unsigned int mask = irq_disable(); \
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*(volatile I##n *)ptr = val; \
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irq_restore(mask); \
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}
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/**
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* @brief This is a macro that defines a function named __atomic_exchange_<em>n</em>
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*
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* @param[in] n width of the data, in bytes
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*/
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#define TEMPLATE_ATOMIC_EXCHANGE_N(n) \
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I##n __atomic_exchange_##n (volatile void *ptr, I##n desired, int memorder) \
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{ \
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(void) memorder; \
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unsigned int mask = irq_disable(); \
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I##n old = *(volatile I##n *)ptr; \
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*(volatile I##n *)ptr = desired; \
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irq_restore(mask); \
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return old; \
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}
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/**
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* @brief This is a macro that defines a function named __atomic_compare_exchange_<em>n</em>
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*
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* @param[in] n width of the data, in bytes
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*/
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#define TEMPLATE_ATOMIC_COMPARE_EXCHANGE_N(n) \
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bool __atomic_compare_exchange_##n (volatile void *ptr, void *expected, I##n desired, \
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bool weak, int success_memorder, int failure_memorder) \
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{ \
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(void) weak; \
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(void) success_memorder; \
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(void) failure_memorder; \
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unsigned int mask = irq_disable(); \
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I##n cur = *(volatile I##n *)ptr; \
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if (cur != *(I##n *)expected) { \
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*(I##n *)expected = cur; \
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irq_restore(mask); \
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return false; \
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} \
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\
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*(volatile I##n *)ptr = desired; \
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irq_restore(mask); \
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return true; \
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}
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/**
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* @brief This is a macro that defines a function named __atomic_fetch_<em>opname</em>_<em>n</em>
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*
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* @param[in] opname operator name that will be used in the function name
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* @param[in] op actual C language operator
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* @param[in] n width of the data, in bytes
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* @param[in] prefixop optional prefix unary operator (use ~ for inverting, NAND, NOR etc)
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*/
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#define TEMPLATE_ATOMIC_FETCH_OP_N(opname, op, n, prefixop) \
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I##n __atomic_fetch_##opname##_##n(volatile void *ptr, I##n val, int memmodel) \
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{ \
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unsigned int mask = irq_disable(); \
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(void)memmodel; \
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I##n tmp = *(volatile I##n *)ptr; \
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*(volatile I##n *)ptr = prefixop(tmp op val); \
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irq_restore(mask); \
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return tmp; \
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}
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/**
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* @brief This is a macro that defines a function named __atomic_<em>opname</em>_fetch_<em>n</em>
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*
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* @param[in] opname operator name that will be used in the function name
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* @param[in] op actual C language operator
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* @param[in] n width of the data, in bytes
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* @param[in] prefixop optional prefix unary operator (use ~ for inverting, NAND, NOR etc)
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*/
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#define TEMPLATE_ATOMIC_OP_FETCH_N(opname, op, n, prefixop) \
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I##n __atomic_##opname##_fetch_##n(volatile void *ptr, I##n val, int memmodel) \
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{ \
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(void)memmodel; \
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unsigned int mask = irq_disable(); \
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I##n tmp = prefixop((*(volatile I##n *)ptr) op val); \
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*(volatile I##n *)ptr = tmp; \
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irq_restore(mask); \
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return tmp; \
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}
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/* Template instantiations below */
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TEMPLATE_ATOMIC_LOAD_N(1) /* __atomic_load_1 */
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TEMPLATE_ATOMIC_LOAD_N(2) /* __atomic_load_2 */
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TEMPLATE_ATOMIC_LOAD_N(4) /* __atomic_load_4 */
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TEMPLATE_ATOMIC_LOAD_N(8) /* __atomic_load_8 */
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TEMPLATE_ATOMIC_STORE_N(1) /* __atomic_store_1 */
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TEMPLATE_ATOMIC_STORE_N(2) /* __atomic_store_2 */
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TEMPLATE_ATOMIC_STORE_N(4) /* __atomic_store_4 */
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TEMPLATE_ATOMIC_STORE_N(8) /* __atomic_store_8 */
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TEMPLATE_ATOMIC_EXCHANGE_N(1) /* __atomic_exchange_1 */
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TEMPLATE_ATOMIC_EXCHANGE_N(2) /* __atomic_exchange_2 */
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TEMPLATE_ATOMIC_EXCHANGE_N(4) /* __atomic_exchange_4 */
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TEMPLATE_ATOMIC_EXCHANGE_N(8) /* __atomic_exchange_8 */
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TEMPLATE_ATOMIC_COMPARE_EXCHANGE_N(1) /* __atomic_compare_exchange_1 */
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TEMPLATE_ATOMIC_COMPARE_EXCHANGE_N(2) /* __atomic_compare_exchange_2 */
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TEMPLATE_ATOMIC_COMPARE_EXCHANGE_N(4) /* __atomic_compare_exchange_4 */
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TEMPLATE_ATOMIC_COMPARE_EXCHANGE_N(8) /* __atomic_compare_exchange_8 */
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TEMPLATE_ATOMIC_FETCH_OP_N( add, +, 1, ) /* __atomic_fetch_add_1 */
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TEMPLATE_ATOMIC_FETCH_OP_N( add, +, 2, ) /* __atomic_fetch_add_2 */
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TEMPLATE_ATOMIC_FETCH_OP_N( add, +, 4, ) /* __atomic_fetch_add_4 */
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TEMPLATE_ATOMIC_FETCH_OP_N( add, +, 8, ) /* __atomic_fetch_add_8 */
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TEMPLATE_ATOMIC_FETCH_OP_N( sub, -, 1, ) /* __atomic_fetch_sub_1 */
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TEMPLATE_ATOMIC_FETCH_OP_N( sub, -, 2, ) /* __atomic_fetch_sub_2 */
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TEMPLATE_ATOMIC_FETCH_OP_N( sub, -, 4, ) /* __atomic_fetch_sub_4 */
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TEMPLATE_ATOMIC_FETCH_OP_N( sub, -, 8, ) /* __atomic_fetch_sub_8 */
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TEMPLATE_ATOMIC_FETCH_OP_N( and, &, 1, ) /* __atomic_fetch_and_1 */
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TEMPLATE_ATOMIC_FETCH_OP_N( and, &, 2, ) /* __atomic_fetch_and_2 */
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TEMPLATE_ATOMIC_FETCH_OP_N( and, &, 4, ) /* __atomic_fetch_and_4 */
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TEMPLATE_ATOMIC_FETCH_OP_N( and, &, 8, ) /* __atomic_fetch_and_8 */
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TEMPLATE_ATOMIC_FETCH_OP_N( or, |, 1, ) /* __atomic_fetch_or_1 */
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TEMPLATE_ATOMIC_FETCH_OP_N( or, |, 2, ) /* __atomic_fetch_or_2 */
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TEMPLATE_ATOMIC_FETCH_OP_N( or, |, 4, ) /* __atomic_fetch_or_4 */
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TEMPLATE_ATOMIC_FETCH_OP_N( or, |, 8, ) /* __atomic_fetch_or_8 */
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TEMPLATE_ATOMIC_FETCH_OP_N( xor, ^, 1, ) /* __atomic_fetch_xor_1 */
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TEMPLATE_ATOMIC_FETCH_OP_N( xor, ^, 2, ) /* __atomic_fetch_xor_2 */
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TEMPLATE_ATOMIC_FETCH_OP_N( xor, ^, 4, ) /* __atomic_fetch_xor_4 */
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TEMPLATE_ATOMIC_FETCH_OP_N( xor, ^, 8, ) /* __atomic_fetch_xor_8 */
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TEMPLATE_ATOMIC_FETCH_OP_N(nand, &, 1, ~) /* __atomic_fetch_nand_1 */
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TEMPLATE_ATOMIC_FETCH_OP_N(nand, &, 2, ~) /* __atomic_fetch_nand_2 */
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TEMPLATE_ATOMIC_FETCH_OP_N(nand, &, 4, ~) /* __atomic_fetch_nand_4 */
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TEMPLATE_ATOMIC_FETCH_OP_N(nand, &, 8, ~) /* __atomic_fetch_nand_8 */
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TEMPLATE_ATOMIC_OP_FETCH_N( add, +, 1, ) /* __atomic_add_fetch_1 */
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TEMPLATE_ATOMIC_OP_FETCH_N( add, +, 2, ) /* __atomic_add_fetch_2 */
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TEMPLATE_ATOMIC_OP_FETCH_N( add, +, 4, ) /* __atomic_add_fetch_4 */
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TEMPLATE_ATOMIC_OP_FETCH_N( add, +, 8, ) /* __atomic_add_fetch_8 */
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TEMPLATE_ATOMIC_OP_FETCH_N( sub, -, 1, ) /* __atomic_sub_fetch_1 */
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TEMPLATE_ATOMIC_OP_FETCH_N( sub, -, 2, ) /* __atomic_sub_fetch_2 */
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TEMPLATE_ATOMIC_OP_FETCH_N( sub, -, 4, ) /* __atomic_sub_fetch_4 */
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TEMPLATE_ATOMIC_OP_FETCH_N( sub, -, 8, ) /* __atomic_sub_fetch_8 */
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TEMPLATE_ATOMIC_OP_FETCH_N( and, &, 1, ) /* __atomic_and_fetch_1 */
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TEMPLATE_ATOMIC_OP_FETCH_N( and, &, 2, ) /* __atomic_and_fetch_2 */
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TEMPLATE_ATOMIC_OP_FETCH_N( and, &, 4, ) /* __atomic_and_fetch_4 */
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TEMPLATE_ATOMIC_OP_FETCH_N( and, &, 8, ) /* __atomic_and_fetch_8 */
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TEMPLATE_ATOMIC_OP_FETCH_N( or, |, 1, ) /* __atomic_or_fetch_1 */
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TEMPLATE_ATOMIC_OP_FETCH_N( or, |, 2, ) /* __atomic_or_fetch_2 */
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TEMPLATE_ATOMIC_OP_FETCH_N( or, |, 4, ) /* __atomic_or_fetch_4 */
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TEMPLATE_ATOMIC_OP_FETCH_N( or, |, 8, ) /* __atomic_or_fetch_8 */
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TEMPLATE_ATOMIC_OP_FETCH_N( xor, ^, 1, ) /* __atomic_xor_fetch_1 */
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TEMPLATE_ATOMIC_OP_FETCH_N( xor, ^, 2, ) /* __atomic_xor_fetch_2 */
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TEMPLATE_ATOMIC_OP_FETCH_N( xor, ^, 4, ) /* __atomic_xor_fetch_4 */
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TEMPLATE_ATOMIC_OP_FETCH_N( xor, ^, 8, ) /* __atomic_xor_fetch_8 */
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TEMPLATE_ATOMIC_OP_FETCH_N(nand, &, 1, ~) /* __atomic_nand_fetch_1 */
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TEMPLATE_ATOMIC_OP_FETCH_N(nand, &, 2, ~) /* __atomic_nand_fetch_2 */
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TEMPLATE_ATOMIC_OP_FETCH_N(nand, &, 4, ~) /* __atomic_nand_fetch_4 */
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TEMPLATE_ATOMIC_OP_FETCH_N(nand, &, 8, ~) /* __atomic_nand_fetch_8 */
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/* ***** Generic versions below ***** */
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/* Clang objects if you redefine a builtin. This little hack allows us to
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* define a function with the same name as an intrinsic. */
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/* Hack origin: http://llvm.org/svn/llvm-project/compiler-rt/trunk/lib/builtins/atomic.c */
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#pragma redefine_extname __atomic_load_c __atomic_load
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#pragma redefine_extname __atomic_store_c __atomic_store
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#pragma redefine_extname __atomic_exchange_c __atomic_exchange
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#pragma redefine_extname __atomic_compare_exchange_c __atomic_compare_exchange
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/**
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* @brief Atomic generic load
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*
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* @param[in] size width of the data, in bytes
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* @param[in] src source address to load from
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* @param[in] dest destination address
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* @param[in] memorder memory ordering, ignored in this implementation
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*/
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void __atomic_load_c(size_t size, const void *src, void *dest, int memorder)
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{
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(void) memorder;
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unsigned int mask = irq_disable();
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memcpy(dest, src, size);
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irq_restore(mask);
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}
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/**
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* @brief Atomic generic store
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*
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* @param[in] size width of the data, in bytes
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* @param[in] dest destination address to store to
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* @param[in] src source address
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* @param[in] memorder memory ordering, ignored in this implementation
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*/
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void __atomic_store_c(size_t size, void *dest, const void *src, int memorder)
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{
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(void) memorder;
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unsigned int mask = irq_disable();
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memcpy(dest, src, size);
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irq_restore(mask);
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}
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/**
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* @brief Atomic generic exchange
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*
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* @param[in] size width of the data, in bytes
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* @param[in] ptr object to swap
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* @param[in] val value to swap to
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* @param[in] ret put the old value from @p ptr in @p ret
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* @param[in] memorder memory ordering, ignored in this implementation
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*/
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void __atomic_exchange_c(size_t size, void *ptr, void *val, void *ret, int memorder)
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{
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(void) memorder;
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unsigned int mask = irq_disable();
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memcpy(ret, ptr, size);
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memcpy(ptr, val, size);
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irq_restore(mask);
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}
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/**
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* @brief Atomic compare-and-swap operation
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*
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* This built-in function implements an atomic compare and exchange operation.
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* This compares the contents of *ptr with the contents of *expected. If equal,
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* the operation is a read-modify-write operation that writes desired into *ptr.
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* If they are not equal, the operation is a read and the current contents of *ptr
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* are written into *expected. weak is true for weak compare_exchange, which may
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* fail spuriously, and false for the strong variation, which never fails
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* spuriously. Many targets only offer the strong variation and ignore the
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* parameter. When in doubt, use the strong variation.
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*
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* If desired is written into *ptr then true is returned and memory is affected
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* according to the memory order specified by success_memorder. There are no
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* restrictions on what memory order can be used here.
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*
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* Otherwise, false is returned and memory is affected according to
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* failure_memorder. This memory order cannot be __ATOMIC_RELEASE nor
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* __ATOMIC_ACQ_REL. It also cannot be a stronger order than that specified by
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* success_memorder.
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*
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* @param[in] len
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* @param[in] ptr
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* @param[in] expected the expected value of ptr
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* @param[in] desired the desired value of ptr
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* @param[in] weak ignored in this implementation
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* @param[in] success_memorder ignored in this implementation
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* @param[in] failure_memorder ignored in this implementation
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*
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* @return true if *ptr had the expected value before the exchange and *ptr was updated
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* @return false otherwise
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*/
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bool __atomic_compare_exchange_c(size_t len, void *ptr, void *expected,
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void *desired, bool weak, int success_memorder, int failure_memorder)
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{
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(void)weak;
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(void)success_memorder;
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(void)failure_memorder;
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unsigned int mask = irq_disable();
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bool ret;
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if (memcmp(ptr, expected, len) == 0) {
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memcpy(ptr, desired, len);
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ret = true;
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}
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else {
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memcpy(expected, ptr, len);
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ret = false;
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}
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irq_restore(mask);
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return ret;
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}
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#if !defined(__llvm__) && !defined(__clang__)
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/* Memory barrier helper function, for platforms without barrier instructions */
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void __sync_synchronize(void) __attribute__((__weak__));
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void __sync_synchronize(void) {
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/* ARMv4, ARMv5 do not have any hardware support for memory barriers,
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* This is a software only barrier and a no-op, and will likely break on SMP
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* systems, but we don't support any multi-CPU ARMv5 or ARMv4 boards in RIOT
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* so I don't care. /JN
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*/
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__asm__ volatile ("" : : : "memory");
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}
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#endif
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/** @} */
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