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https://github.com/RIOT-OS/RIOT.git
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e2489ced97
Add some register values needed to trim registers. Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
93 lines
2.5 KiB
C
93 lines
2.5 KiB
C
/*
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* Copyright (C) 2016 Leon George
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_cc26xx_cc13xx_definitions
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* @{
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*
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* @file
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* @brief CC26xx/CC13xx CCFG register definitions
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*/
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#ifndef CC26XX_CC13XX_CCFG_H
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#define CC26XX_CC13XX_CCFG_H
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#include <cc26xx_cc13xx.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief CCFG registers
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*/
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typedef struct {
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reg32_t EXT_LF_CLK; /**< extern LF clock config */
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reg32_t MODE_CONF_1; /**< mode config 1 */
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reg32_t SIZE_AND_DIS_FLAGS; /**< CCFG size and disable flags */
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reg32_t MODE_CONF; /**< mmode config 0 */
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reg32_t VOLT_LOAD_0; /**< voltage load 0 */
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reg32_t VOLT_LOAD_1; /**< voltage load 1 */
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reg32_t RTC_OFFSET; /**< RTC offset */
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reg32_t FREQ_OFFSET; /**< frequency offset */
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reg32_t IEEE_MAC_0; /**< IEEE MAC address 0 */
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reg32_t IEEE_MAC_1; /**< IEEE MAC address 1 */
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reg32_t IEEE_BLE_0; /**< IEEE BLE address 0 */
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reg32_t IEEE_BLE_1; /**< IEEE BLE address 1 */
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reg32_t BL_CONFIG; /**< bootloader config */
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reg32_t ERASE_CONF; /**< erase config */
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reg32_t CCFG_TI_OPTIONS; /**< TI options */
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reg32_t CCFG_TAP_DAP_0; /**< test access points enable 0 */
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reg32_t CCFG_TAP_DAP_1; /**< test access points enable 1 */
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reg32_t IMAGE_VALID_CONF; /**< image valid */
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reg32_t CCFG_PROT_31_0; /**< protect sectors 0-31 */
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reg32_t CCFG_PROT_63_32; /**< protect sectors 32-63 */
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reg32_t CCFG_PROT_95_64; /**< protect sectors 64-95 */
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reg32_t CCFG_PROT_127_96; /**< protect sectors 96-127 */
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} ccfg_regs_t;
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/**
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* @brief CCFG register values
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* @{
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*/
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#define CCFG_MODE_CONF_1_ALT_DCDC_IPEAK_s 16
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#define CCFG_MODE_CONF_VDDR_EXT_LOAD 0x02000000
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#define CCFG_MODE_CONF_VDDS_BOD_LEVEL 0x01000000
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#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004
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#define CCFG_SIZE_AND_DIS_FLAGS_DIS_ALT_DCDC_SETTING 0x00000002
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/** @} */
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/**
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* @ingroup cpu_specific_peripheral_memory_map
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* @{
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*/
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/**
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* @brief CCFG base address
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*/
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#define CCFG_BASE (0x50003000)
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/** @} */
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#ifdef CPU_VARIANT_X0
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/**
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* @brief CCFG register bank
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*/
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#define CCFG ((ccfg_regs_t *) (CCFG_BASE + 0xFA8))
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#else
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/**
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* @brief CCFG register bank
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*/
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#define CCFG ((ccfg_regs_t *) (CCFG_BASE + 0x1FA8))
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#endif
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#ifdef __cplusplus
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} /* end extern "C" */
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#endif
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#endif /* CC26XX_CC13XX_CCFG_H */
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/** @} */
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