mirror of
https://github.com/RIOT-OS/RIOT.git
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5a3326350b
- nucleo-f334r8: - Added USART1 and USART3 config - nucleo-f401re: - Changed order of UARTs to match the other boards - nucleo-f410rb: - Added USART6 configuration - Fixed incorrect DMA settings (according to reference manual of the MCU) - nucleo-f446re: - Changed order of UARTs to match the other boards - nucleo-l152re: - Changed order of UARTs to match the other boards The result of this harmonization is, that the first UART is always USART2, the other USARTs are added in ascending order.
268 lines
6.8 KiB
C
268 lines
6.8 KiB
C
/*
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* Copyright (C) 2016 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @defgroup boards_nucleo-f446re STM32 Nucleo-F446RE
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* @ingroup boards_common_nucleo64
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* @brief Support for the STM32 Nucleo-F446RE
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the nucleo-f446re board
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "f4/cfg_clock_180_8_1.h"
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#include "cfg_spi_divtable.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM5,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM5EN,
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.bus = APB1,
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.irqn = TIM5_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim5
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#define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0]))
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 3),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 6,
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.dma_chan = 4
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#endif
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},
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_A, 10),
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.tx_pin = GPIO_PIN(PORT_A, 9),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB2,
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.irqn = USART1_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 4,
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.dma_chan = 4
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#endif
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},
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{
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.dev = USART3,
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.rcc_mask = RCC_APB1ENR_USART3EN,
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.rx_pin = GPIO_PIN(PORT_C, 11),
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.tx_pin = GPIO_PIN(PORT_C, 10),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART3_IRQn,
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#ifdef UART_USE_DMA
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.dma_stream = 5,
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.dma_chan = 4
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#endif
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},
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};
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#define UART_0_ISR (isr_usart2)
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#define UART_0_DMA_ISR (isr_dma1_stream6)
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#define UART_1_ISR (isr_usart1)
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#define UART_1_DMA_ISR (isr_dma1_stream4)
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#define UART_2_ISR (isr_usart3)
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#define UART_2_DMA_ISR (isr_dma1_stream5)
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#define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0]))
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.dev = TIM2,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0},
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{ .pin = GPIO_PIN(PORT_B, 3), .cc_chan = 1},
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{ .pin = GPIO_PIN(PORT_B, 10), .cc_chan = 2},
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{ .pin = GPIO_PIN(PORT_B, 2), .cc_chan = 3} },
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.af = GPIO_AF1,
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.bus = APB1
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},
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{
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.dev = TIM8,
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.rcc_mask = RCC_APB2ENR_TIM8EN,
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.chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0},
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{ .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1},
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{ .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2},
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{ .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} },
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.af = GPIO_AF3,
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.bus = APB2
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},
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};
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#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
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/** @} */
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/**
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* @name QDEC configuration
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* @{
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*/
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static const qdec_conf_t qdec_config[] = {
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{
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.dev = TIM3,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM3EN,
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.chan = { { .pin = GPIO_PIN(PORT_A, 6), .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_A, 7), .cc_chan = 1 } },
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.af = GPIO_AF2,
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.bus = APB1,
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.irqn = TIM3_IRQn
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},
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{
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.dev = TIM4,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM4EN,
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.chan = { { .pin = GPIO_PIN(PORT_B, 6), .cc_chan = 0 },
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{ .pin = GPIO_PIN(PORT_B, 7), .cc_chan = 1 } },
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.af = GPIO_AF2,
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.bus = APB1,
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.irqn = TIM4_IRQn
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},
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};
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#define QDEC_0_ISR isr_tim3
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#define QDEC_1_ISR isr_tim4
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#define QDEC_NUMOF (sizeof(qdec_config) / sizeof(qdec_config[0]))
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_PIN(PORT_A, 4),
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.af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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},
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{
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.dev = SPI2,
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.mosi_pin = GPIO_PIN(PORT_B, 15),
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.miso_pin = GPIO_PIN(PORT_B, 14),
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.sclk_pin = GPIO_PIN(PORT_B, 13),
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.cs_pin = GPIO_PIN(PORT_B, 12),
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.af = GPIO_AF5,
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.rccmask = RCC_APB1ENR_SPI2EN,
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.apbbus = APB1
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},
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{
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.dev = SPI3,
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.mosi_pin = GPIO_PIN(PORT_C, 12),
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.miso_pin = GPIO_PIN(PORT_C, 11),
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.sclk_pin = GPIO_PIN(PORT_C, 10),
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.cs_pin = GPIO_UNDEF,
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.af = GPIO_AF6,
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.rccmask = RCC_APB1ENR_SPI3EN,
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.apbbus = APB1
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}
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};
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.dev = I2C1,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_B, 8),
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.sda_pin = GPIO_PIN(PORT_B, 9),
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.scl_af = GPIO_AF4,
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.sda_af = GPIO_AF4,
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.bus = APB1,
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.rcc_mask = RCC_APB1ENR_I2C1EN,
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.clk = CLOCK_APB1,
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.irqn = I2C1_EV_IRQn
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}
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};
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#define I2C_0_ISR isr_i2c1_ev
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#define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0]))
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/** @} */
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/**
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* @name ADC configuration
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*
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* Note that we do not configure all ADC channels,
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* and not in the STM32F446 order. Instead, we
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* just define 6 ADC channels, for the Nucleo
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* Arduino header pins A0-A5
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*
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* @{
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*/
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#define ADC_NUMOF (6U)
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#define ADC_CONFIG { \
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{GPIO_PIN(PORT_A, 0), 0, 0}, \
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{GPIO_PIN(PORT_A, 1), 0, 1}, \
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{GPIO_PIN(PORT_A, 4), 0, 4}, \
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{GPIO_PIN(PORT_B, 0), 0, 8}, \
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{GPIO_PIN(PORT_C, 1), 0, 11}, \
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{GPIO_PIN(PORT_C, 0), 0, 10}, \
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}
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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