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d37adee32d
There is no hardware limitation for custom boards based on STM32 to uses SPI bus with signals coming from different PORT and alternate functions. This patch allow alternate's function definition per pin basis, thus enable the support of SPI bus signals routed on differents PORT. Signed-off-by: Yannick Gicquel <ygicquel@gmail.com>
176 lines
4.2 KiB
C
176 lines
4.2 KiB
C
/*
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* Copyright (C) 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_lsn50
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the LSN50 board
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "l0/cfg_clock_32_16_1.h"
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#include "cfg_rtt_default.h"
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#include "cfg_timer_tim2.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name DMA streams configuration
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* @{
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*/
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#ifdef MODULE_PERIPH_DMA
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static const dma_conf_t dma_config[] = {
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{ .stream = 1 }, /* channel 2 */
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{ .stream = 2 }, /* channel 3 */
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{ .stream = 3 }, /* channel 4 */
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{ .stream = 4 }, /* channel 5 */
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{ .stream = 5 }, /* channel 6 */
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};
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#define DMA_SHARED_ISR_0 isr_dma1_channel2_3
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#define DMA_SHARED_ISR_0_STREAMS { 0, 1 } /* Indexes 0 and 1 of dma_config share the same isr */
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#define DMA_SHARED_ISR_1 isr_dma1_channel4_5_6_7
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#define DMA_SHARED_ISR_1_STREAMS { 2, 3, 4 } /* Indexes 2, 3 and 4 of dma_config share the same isr */
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#define DMA_NUMOF ARRAY_SIZE(dma_config)
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#endif
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_A, 10),
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.tx_pin = GPIO_PIN(PORT_A, 9),
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.rx_af = GPIO_AF4,
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.tx_af = GPIO_AF4,
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.bus = APB2,
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.irqn = USART1_IRQn,
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.type = STM32_USART,
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.clk_src = 0, /* Use APB clock */
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#ifdef MODULE_PERIPH_DMA
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.dma = 0,
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.dma_chan = 3,
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#endif
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},
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{
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 3),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.rx_af = GPIO_AF4,
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.tx_af = GPIO_AF4,
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.bus = APB1,
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.irqn = USART2_IRQn,
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.type = STM32_USART,
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.clk_src = 0, /* Use APB clock */
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#ifdef MODULE_PERIPH_DMA
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.dma = 2,
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.dma_chan = 4,
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#endif
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},
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};
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#define UART_0_ISR (isr_usart1)
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#define UART_1_ISR (isr_usart2)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 32000000Hz */
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7, /* -> 125000Hz */
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5, /* -> 500000Hz */
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4, /* -> 1000000Hz */
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2, /* -> 4000000Hz */
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1 /* -> 8000000Hz */
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},
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{ /* for APB2 @ 32000000Hz */
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7, /* -> 125000Hz */
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5, /* -> 500000Hz */
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4, /* -> 1000000Hz */
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2, /* -> 4000000Hz */
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1 /* -> 8000000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1, /* connected to SX1276 */
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_UNDEF,
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.mosi_af = GPIO_AF0,
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.miso_af = GPIO_AF0,
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.sclk_af = GPIO_AF0,
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.cs_af = GPIO_AF0,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2,
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#ifdef MODULE_PERIPH_DMA
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.tx_dma = 1,
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.tx_dma_chan = 1,
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.rx_dma = 0,
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.rx_dma_chan = 1,
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#endif
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},
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{
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.dev = I2C1,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_B, 6),
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.sda_pin = GPIO_PIN(PORT_B, 7),
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.scl_af = GPIO_AF4,
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.sda_af = GPIO_AF4,
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.bus = APB1,
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.rcc_mask = RCC_APB1ENR_I2C1EN,
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.irqn = I2C1_IRQn
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}
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};
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#define I2C_0_ISR isr_i2c1
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#define I2C_NUMOF ARRAY_SIZE(i2c_config)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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