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https://github.com/RIOT-OS/RIOT.git
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287 lines
8.1 KiB
C
287 lines
8.1 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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* Copyright (C) 2015 PHYTEC Messtechnik GmbH
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup board_frdm-k64f
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the FRDM-K64F
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*
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* @author Johann Fischer <j.fischer@phytec.de>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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#define KINETIS_CPU_USE_MCG 1
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#define KINETIS_MCG_USE_ERC 1
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#define KINETIS_MCG_USE_PLL 1
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#define KINETIS_MCG_DCO_RANGE (24000000U)
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#define KINETIS_MCG_ERC_OSCILLATOR 0
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#define KINETIS_MCG_ERC_FRDIV 6 /* ERC devider = 1280 */
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#define KINETIS_MCG_ERC_RANGE 2
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#define KINETIS_MCG_ERC_FREQ 50000000
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#define KINETIS_MCG_PLL_PRDIV 19 /* divide factor = 20 */
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#define KINETIS_MCG_PLL_VDIV0 0 /* multiply factor = 24 */
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#define KINETIS_MCG_PLL_FREQ 60000000
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#define CLOCK_CORECLOCK KINETIS_MCG_PLL_FREQ
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#define CLOCK_BUSCLOCK (CLOCK_CORECLOCK / 2)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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#define PIT_NUMOF (2U)
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#define PIT_CONFIG { \
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{ \
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.prescaler_ch = 0, \
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.count_ch = 1, \
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}, \
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{ \
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.prescaler_ch = 2, \
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.count_ch = 3, \
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}, \
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}
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#define LPTMR_NUMOF (0U)
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#define LPTMR_CONFIG {}
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#define TIMER_NUMOF ((PIT_NUMOF) + (LPTMR_NUMOF))
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#define PIT_BASECLOCK (CLOCK_BUSCLOCK)
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#define PIT_CLOCKGATE (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_PIT_SHIFT))
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#define PIT_ISR_0 isr_pit1
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#define PIT_ISR_1 isr_pit3
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#define LPTMR_ISR_0 isr_lptmr0
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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#define UART_NUMOF (1U)
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#define UART_0_EN 1
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#define UART_IRQ_PRIO 1
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#define UART_CLK CLOCK_CORECLOCK
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/* UART 0 device configuration */
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#define KINETIS_UART UART_Type
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#define UART_0_DEV UART0
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#define UART_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_UART0_MASK))
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#define UART_0_CLK UART_CLK
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#define UART_0_IRQ_CHAN UART0_RX_TX_IRQn
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#define UART_0_ISR isr_uart0_rx_tx
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/* UART 0 pin configuration */
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#define UART_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK))
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#define UART_0_PORT PORTB
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#define UART_0_RX_PIN 16
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#define UART_0_TX_PIN 17
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#define UART_0_AF 3
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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static const adc_conf_t adc_config[] = {
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/* dev, pin, channel */
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{ ADC0, GPIO_PIN(PORT_B, 10), 14 },
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{ ADC0, GPIO_PIN(PORT_B, 11), 15 },
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{ ADC0, GPIO_PIN(PORT_C, 11), 7 },
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{ ADC0, GPIO_PIN(PORT_C, 10), 6 },
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{ ADC0, GPIO_PIN(PORT_C, 8), 4 },
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{ ADC0, GPIO_PIN(PORT_C, 9), 5 },
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};
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#define ADC_NUMOF (sizeof(adc_config) / sizeof(adc_config[0]))
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/** @} */
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/**
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* @name DAC configuration
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* @{
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*/
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#define DAC_CONFIG {}
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#define DAC_NUMOF 0
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/** @} */
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/**
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* @brief PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.ftm = FTM0,
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.chan = {
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{ .pin = GPIO_PIN(PORT_A, 4), .af = 3, .ftm_chan = 6 },
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{ .pin = GPIO_PIN(PORT_A, 2), .af = 3, .ftm_chan = 7 },
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{ .pin = GPIO_PIN(PORT_C, 2), .af = 4, .ftm_chan = 1 },
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{ .pin = GPIO_PIN(PORT_C, 3), .af = 4, .ftm_chan = 2 }
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},
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.chan_numof = 4,
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.ftm_num = 0
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}
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};
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#define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0]))
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/** @} */
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/**
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* @name SPI configuration
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*
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* Clock configuration values based on the configured 30Mhz module clock.
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*
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* Auto-generated by:
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* cpu/kinetis_common/dist/calc_spi_scalers/calc_spi_scalers.c
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*
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* @{
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*/
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static const uint32_t spi_clk_config[] = {
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(
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SPI_CTAR_PBR(2) | SPI_CTAR_BR(6) | /* -> 93750Hz */
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SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(5) |
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SPI_CTAR_PASC(2) | SPI_CTAR_ASC(5) |
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SPI_CTAR_PDT(2) | SPI_CTAR_DT(5)
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),
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(
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SPI_CTAR_PBR(2) | SPI_CTAR_BR(4) | /* -> 375000Hz */
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SPI_CTAR_PCSSCK(2) | SPI_CTAR_CSSCK(3) |
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SPI_CTAR_PASC(2) | SPI_CTAR_ASC(3) |
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SPI_CTAR_PDT(2) | SPI_CTAR_DT(3)
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),
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(
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SPI_CTAR_PBR(2) | SPI_CTAR_BR(2) | /* -> 1000000Hz */
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SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(4) |
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SPI_CTAR_PASC(0) | SPI_CTAR_ASC(4) |
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SPI_CTAR_PDT(0) | SPI_CTAR_DT(4)
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),
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(
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SPI_CTAR_PBR(1) | SPI_CTAR_BR(0) | /* -> 5000000Hz */
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SPI_CTAR_PCSSCK(1) | SPI_CTAR_CSSCK(0) |
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SPI_CTAR_PASC(1) | SPI_CTAR_ASC(0) |
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SPI_CTAR_PDT(1) | SPI_CTAR_DT(0)
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),
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(
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SPI_CTAR_PBR(0) | SPI_CTAR_BR(0) | /* -> 7500000Hz */
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SPI_CTAR_PCSSCK(0) | SPI_CTAR_CSSCK(1) |
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SPI_CTAR_PASC(0) | SPI_CTAR_ASC(1) |
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SPI_CTAR_PDT(0) | SPI_CTAR_DT(1)
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)
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI0,
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.pin_miso = GPIO_PIN(PORT_D, 3),
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.pin_mosi = GPIO_PIN(PORT_D, 2),
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.pin_clk = GPIO_PIN(PORT_D, 1),
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.pin_cs = {
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GPIO_PIN(PORT_D, 0),
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GPIO_UNDEF,
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GPIO_UNDEF,
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GPIO_UNDEF,
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GPIO_UNDEF
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},
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.pcr = GPIO_AF_2,
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.simmask = SIM_SCGC6_SPI0_MASK
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}
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};
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#define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0]))
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (1U)
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#define I2C_CLK CLOCK_CORECLOCK
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#define I2C_0_EN 1
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#define I2C_IRQ_PRIO 1
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/* Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 */
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#define KINETIS_I2C_F_ICR_LOW (0x3D)
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#define KINETIS_I2C_F_MULT_LOW (2)
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/* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
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#define KINETIS_I2C_F_ICR_NORMAL (0x1F)
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#define KINETIS_I2C_F_MULT_NORMAL (1)
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/* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
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#define KINETIS_I2C_F_ICR_FAST (0x17)
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#define KINETIS_I2C_F_MULT_FAST (0)
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/* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
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#define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
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#define KINETIS_I2C_F_MULT_FAST_PLUS (0)
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C0
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#define I2C_0_CLKEN() (SIM->SCGC4 |= (SIM_SCGC4_I2C0_MASK))
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#define I2C_0_CLKDIS() (SIM->SCGC4 &= ~(SIM_SCGC4_I2C0_MASK))
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#define I2C_0_IRQ I2C0_IRQn
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#define I2C_0_IRQ_HANDLER isr_i2c0
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/* I2C 0 pin configuration */
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#define I2C_0_PORT PORTE
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#define I2C_0_PORT_CLKEN() (SIM->SCGC5 |= (SIM_SCGC5_PORTE_MASK))
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#define I2C_0_PIN_AF 5
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#define I2C_0_SDA_PIN 25
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#define I2C_0_SCL_PIN 24
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#define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
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/** @} */
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/**
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* @name GPIO configuration
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* @{
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*/
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#define GPIO_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
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/** @} */
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/**
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* @name RTT and RTC configuration
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* @{
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*/
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#define RTT_NUMOF (1U)
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#define RTC_NUMOF (1U)
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#define RTT_DEV RTC
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#define RTT_IRQ RTC_IRQn
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#define RTT_IRQ_PRIO 10
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#define RTT_UNLOCK() (SIM->SCGC6 |= (SIM_SCGC6_RTC_MASK))
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#define RTT_ISR isr_rtc
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#define RTT_FREQUENCY (1)
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#define RTT_MAX_VALUE (0xffffffff)
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/** @} */
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/**
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* @name Random Number Generator configuration
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* @{
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*/
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#define KINETIS_RNGA RNG
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#define HWRNG_CLKEN() (SIM->SCGC6 |= (1 << 9))
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#define HWRNG_CLKDIS() (SIM->SCGC6 &= ~(1 << 9))
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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