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56 lines
2.8 KiB
Plaintext
56 lines
2.8 KiB
Plaintext
/**
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* @defgroup cpu_stm32_common STM32 common
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* @ingroup cpu
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* @brief STM32 common code and definitions
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*
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* This module contains all common code and definition to all STM32 cpu
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* families supported by RIOT: @ref cpu_stm32f0, @ref cpu_stm32l0,
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* @ref cpu_stm32f1, @ref cpu_stm32f2, @ref cpu_stm32f3, @ref cpu_stm32f4,
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* @ref cpu_stm32l4, @ref cpu_stm32f7.
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*
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* STM32Fx Clock configuration
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* =================================
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*
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* stm32fx cpus share clock configuration code and macro.
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* It can be configured as described here.
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*
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* The following macro must be defined in the board's periph_conf.h:
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* - CLOCK_HSE: 0 if HSI must be used as PLL source, frequency in Hz otherwise,
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* - CLOCK_LSE: 0 if LSI must be used as low speed clock, 1 otherwise
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* (the LSE is a 32.768kHz crytal)
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* - CLOCK_CORECLOCK: desired main clock frequency
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* - CLOCK_AHB_DIV, CLOCK_AHB: AHB prescaler in register value and AHB frequecny in Hz
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* - CLOCK_APB1_DIV, CLOCK_APB1: APB1 prescaler in register value and APB1 frequecny in Hz
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* - CLOCK_APB2_DIV, CLOCK_APB2: APB2 prescaler in register value and APB2 frequecny in Hz
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* (CLOCK_APB2_DIV is not needed for stm32f0)
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*
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* The following macro must be defined for stm32f[2|4|7]:
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* - CLOCK_PLL_M, CLOCK_PLL_N, CLOCK_PLL_P, CLOCK_PLL_Q, (CLOCK_PLL_R, optional):
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* Main PLL factors
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*
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* The following macro must be defined for stm32f[0|1|3]:
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* - PLL_MUL, PLL_PREDIV: PLL factors. These values are used as is. A PREDIV of 2
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* can be assumed when HSI is selected as PLL input. Some model support any value
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* as PREDIV even with HSI though. The `clk_conf` tool will assume PREDIV must be
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* to with HSI and will set it accordingly.
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*
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* The following macro are optional and can be defined depending on board config
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* and application needs:
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* - CLOCK_ENABLE_PLL_I2S: if a second PLL (PLL I2S) is available on the cpu, it
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* can be activated with this macro, then CLOCK_PLL_I2S_M, CLOCK_PLL_I2S_N,
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* CLOCK_PLL_I2S_P and CLOCK_PLL_I2S_Q need to be defined, CLOCK_PLL_I2S_R is optional.
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* - CLOCK_ENABLE_PLL_SAI: if a second PLL (PLL SAI) is available on the cpu, it
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* can be activated with this macro, then CLOCK_PLL_SAI_M, CLOCK_PLL_SAI_N,
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* CLOCK_PLL_SAI_P and CLOCK_PLL_SAI_Q need to be defined, CLOCK_PLL_SAI_R is optional.
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* - CLOCK_USE_ALT_48MHZ: if the 48MHz clock should be generated by the alternate
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* source (PLL I2S or PLL SAI, depending on cpu)
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*
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* All the previous constants can be generated using the tool in
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* `cpu/stm32_common/dist/clk_conf`.
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*
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* Clock outputs can also be setup with macro:
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* - CLOCK_MCOx_SRC, CLOCK_MCOx_PRE, with x=1,2: MCO1 and MCO2 output configuration
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* macros. CLOCK_MCOx_SRC defines the MCOx source, as a register value (see vendor header),
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* CLOCK_MCOx_PRE defines the MCOx prescaler, as a register value.
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*/
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