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https://github.com/RIOT-OS/RIOT.git
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121 lines
3.0 KiB
C
121 lines
3.0 KiB
C
/*
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* Copyright (C) 2020 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Configure STM32G0/G4 clock
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*
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* CORECLOCK cannot exceeds 64MHz core clock. LSE is 32768Hz.
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* Default configuration use PLL clock as system clock. PLL input clock is HSI
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* by default.
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef CLK_G0G4_CFG_CLOCK_DEFAULT_H
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#define CLK_G0G4_CFG_CLOCK_DEFAULT_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name G0/G4 clock settings
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*
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* @{
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*/
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CLOCK_HSE < MHZ(4) || CLOCK_HSE > MHZ(48))
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#error "HSE clock frequency must be between 4MHz and 48MHz"
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#endif
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#ifdef CPU_FAM_STM32G0
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#ifndef CONFIG_CLOCK_HSISYS_DIV
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#define CONFIG_CLOCK_HSISYS_DIV (1)
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#endif
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#endif
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#define CLOCK_PLL_SRC (CLOCK_HSE)
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#else /* CLOCK_HSI */
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#define CLOCK_PLL_SRC (CLOCK_HSI)
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#endif
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/* The following parameters configure a 64MHz system clock with HSI as input clock */
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#ifndef CONFIG_CLOCK_PLL_M
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#ifdef CPU_FAM_STM32G0
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#define CONFIG_CLOCK_PLL_M (1)
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#else
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#define CONFIG_CLOCK_PLL_M (4)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_N
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#ifdef CPU_FAM_STM32G0
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#define CONFIG_CLOCK_PLL_N (20)
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#else
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#define CONFIG_CLOCK_PLL_N (85)
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_R
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#ifdef CPU_FAM_STM32G0
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#define CONFIG_CLOCK_PLL_R (5)
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#else
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#define CONFIG_CLOCK_PLL_R (2)
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#endif
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#endif
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
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#ifdef CPU_FAM_STM32G0
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#define CLOCK_CORECLOCK (CLOCK_HSI / CONFIG_CLOCK_HSISYS_DIV)
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#else
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#define CLOCK_CORECLOCK (CLOCK_HSI)
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#endif
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#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
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#if !IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#error "The board doesn't provide an HSE oscillator"
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#endif
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#define CLOCK_CORECLOCK (CLOCK_HSE)
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#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
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#define CLOCK_CORECLOCK \
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((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
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#ifdef CPU_FAM_STM32G0
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#if CLOCK_CORECLOCK > MHZ(64)
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#error "SYSCLK cannot exceed 64MHz"
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#endif
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#else /* CPU_FAM_STM32G4 */
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#if CLOCK_CORECLOCK > MHZ(170)
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#error "SYSCLK cannot exceed 170MHz"
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#endif
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#endif
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#endif /* CONFIG_USE_CLOCK_PLL */
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#define CLOCK_AHB CLOCK_CORECLOCK /* max: 64MHz (G0), 170MHZ (G4) */
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (1)
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#endif
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#define CLOCK_APB1 (CLOCK_CORECLOCK / CONFIG_CLOCK_APB1_DIV) /* max: 64MHz (G0), 170MHZ (G4) */
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#ifdef CPU_FAM_STM32G4
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (1)
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#endif
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#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* max: 170MHz (only on G4) */
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#endif
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CLK_G0G4_CFG_CLOCK_DEFAULT_H */
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/** @} */
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