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236 lines
16 KiB
C
236 lines
16 KiB
C
/**
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* \file
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*
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* \brief Component description for GCLK
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*
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* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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/*
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* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
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*/
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#ifndef _SAML21_GCLK_COMPONENT_
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#define _SAML21_GCLK_COMPONENT_
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/* ========================================================================== */
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/** SOFTWARE API DEFINITION FOR GCLK */
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/* ========================================================================== */
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/** \addtogroup SAML21_GCLK Generic Clock Generator */
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/*@{*/
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#define GCLK_U2122
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#define REV_GCLK 0x111
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/* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint8_t SWRST:1; /*!< bit: 0 Software Reset */
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uint8_t :7; /*!< bit: 1.. 7 Reserved */
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} bit; /*!< Structure used for bit access */
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uint8_t reg; /*!< Type used for register access */
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} GCLK_CTRLA_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define GCLK_CTRLA_OFFSET 0x00 /**< \brief (GCLK_CTRLA offset) Control */
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#define GCLK_CTRLA_RESETVALUE 0x00ul /**< \brief (GCLK_CTRLA reset_value) Control */
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#define GCLK_CTRLA_SWRST_Pos 0 /**< \brief (GCLK_CTRLA) Software Reset */
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#define GCLK_CTRLA_SWRST (0x1ul << GCLK_CTRLA_SWRST_Pos)
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#define GCLK_CTRLA_MASK 0x01ul /**< \brief (GCLK_CTRLA) MASK Register */
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/* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) (R/ 32) Synchronization Busy -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchroniation Busy bit */
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uint32_t :1; /*!< bit: 1 Reserved */
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uint32_t GENCTRL:9; /*!< bit: 2..10 Generic Clock Generator Control Synchronization Busy bits */
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uint32_t :21; /*!< bit: 11..31 Reserved */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} GCLK_SYNCBUSY_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define GCLK_SYNCBUSY_OFFSET 0x04 /**< \brief (GCLK_SYNCBUSY offset) Synchronization Busy */
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#define GCLK_SYNCBUSY_RESETVALUE 0x00000000ul /**< \brief (GCLK_SYNCBUSY reset_value) Synchronization Busy */
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#define GCLK_SYNCBUSY_SWRST_Pos 0 /**< \brief (GCLK_SYNCBUSY) Software Reset Synchroniation Busy bit */
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#define GCLK_SYNCBUSY_SWRST (0x1ul << GCLK_SYNCBUSY_SWRST_Pos)
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#define GCLK_SYNCBUSY_GENCTRL_Pos 2 /**< \brief (GCLK_SYNCBUSY) Generic Clock Generator Control Synchronization Busy bits */
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#define GCLK_SYNCBUSY_GENCTRL_Msk (0x1FFul << GCLK_SYNCBUSY_GENCTRL_Pos)
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#define GCLK_SYNCBUSY_GENCTRL(value) ((GCLK_SYNCBUSY_GENCTRL_Msk & ((value) << GCLK_SYNCBUSY_GENCTRL_Pos)))
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#define GCLK_SYNCBUSY_GENCTRL_GCLK0_Val 0x0ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 0 */
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#define GCLK_SYNCBUSY_GENCTRL_GCLK1_Val 0x1ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 1 */
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#define GCLK_SYNCBUSY_GENCTRL_GCLK2_Val 0x2ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 2 */
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#define GCLK_SYNCBUSY_GENCTRL_GCLK3_Val 0x3ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 3 */
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#define GCLK_SYNCBUSY_GENCTRL_GCLK4_Val 0x4ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 4 */
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#define GCLK_SYNCBUSY_GENCTRL_GCLK5_Val 0x5ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 5 */
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#define GCLK_SYNCBUSY_GENCTRL_GCLK6_Val 0x6ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 6 */
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#define GCLK_SYNCBUSY_GENCTRL_GCLK7_Val 0x7ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 7 */
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#define GCLK_SYNCBUSY_GENCTRL_GCLK8_Val 0x8ul /**< \brief (GCLK_SYNCBUSY) Generic clock generator 8 */
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#define GCLK_SYNCBUSY_GENCTRL_GCLK0 (GCLK_SYNCBUSY_GENCTRL_GCLK0_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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#define GCLK_SYNCBUSY_GENCTRL_GCLK1 (GCLK_SYNCBUSY_GENCTRL_GCLK1_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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#define GCLK_SYNCBUSY_GENCTRL_GCLK2 (GCLK_SYNCBUSY_GENCTRL_GCLK2_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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#define GCLK_SYNCBUSY_GENCTRL_GCLK3 (GCLK_SYNCBUSY_GENCTRL_GCLK3_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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#define GCLK_SYNCBUSY_GENCTRL_GCLK4 (GCLK_SYNCBUSY_GENCTRL_GCLK4_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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#define GCLK_SYNCBUSY_GENCTRL_GCLK5 (GCLK_SYNCBUSY_GENCTRL_GCLK5_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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#define GCLK_SYNCBUSY_GENCTRL_GCLK6 (GCLK_SYNCBUSY_GENCTRL_GCLK6_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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#define GCLK_SYNCBUSY_GENCTRL_GCLK7 (GCLK_SYNCBUSY_GENCTRL_GCLK7_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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#define GCLK_SYNCBUSY_GENCTRL_GCLK8 (GCLK_SYNCBUSY_GENCTRL_GCLK8_Val << GCLK_SYNCBUSY_GENCTRL_Pos)
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#define GCLK_SYNCBUSY_MASK 0x000007FDul /**< \brief (GCLK_SYNCBUSY) MASK Register */
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/* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t SRC:4; /*!< bit: 0.. 3 Source Select */
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uint32_t :4; /*!< bit: 4.. 7 Reserved */
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uint32_t GENEN:1; /*!< bit: 8 Generic Clock Generator Enable */
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uint32_t IDC:1; /*!< bit: 9 Improve Duty Cycle */
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uint32_t OOV:1; /*!< bit: 10 Output Off Value */
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uint32_t OE:1; /*!< bit: 11 Output Enable */
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uint32_t DIVSEL:1; /*!< bit: 12 Divide Selection */
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uint32_t RUNSTDBY:1; /*!< bit: 13 Run in Standby */
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uint32_t :2; /*!< bit: 14..15 Reserved */
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uint32_t DIV:16; /*!< bit: 16..31 Division Factor */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} GCLK_GENCTRL_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define GCLK_GENCTRL_OFFSET 0x20 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */
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#define GCLK_GENCTRL_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */
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#define GCLK_GENCTRL_SRC_Pos 0 /**< \brief (GCLK_GENCTRL) Source Select */
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#define GCLK_GENCTRL_SRC_Msk (0xFul << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_SRC(value) ((GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos)))
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#define GCLK_GENCTRL_SRC_XOSC_Val 0x0ul /**< \brief (GCLK_GENCTRL) XOSC oscillator output */
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#define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1ul /**< \brief (GCLK_GENCTRL) Generator input pad */
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#define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2ul /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */
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#define GCLK_GENCTRL_SRC_OSCULP32K_Val 0x3ul /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */
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#define GCLK_GENCTRL_SRC_OSC32K_Val 0x4ul /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */
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#define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5ul /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */
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#define GCLK_GENCTRL_SRC_OSC16M_Val 0x6ul /**< \brief (GCLK_GENCTRL) OSC16M oscillator output */
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#define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7ul /**< \brief (GCLK_GENCTRL) DFLL48M output */
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#define GCLK_GENCTRL_SRC_DPLL96M_Val 0x8ul /**< \brief (GCLK_GENCTRL) DPLL96M output */
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#define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_SRC_OSC16M (GCLK_GENCTRL_SRC_OSC16M_Val << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_SRC_DPLL96M (GCLK_GENCTRL_SRC_DPLL96M_Val << GCLK_GENCTRL_SRC_Pos)
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#define GCLK_GENCTRL_GENEN_Pos 8 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */
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#define GCLK_GENCTRL_GENEN (0x1ul << GCLK_GENCTRL_GENEN_Pos)
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#define GCLK_GENCTRL_IDC_Pos 9 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */
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#define GCLK_GENCTRL_IDC (0x1ul << GCLK_GENCTRL_IDC_Pos)
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#define GCLK_GENCTRL_OOV_Pos 10 /**< \brief (GCLK_GENCTRL) Output Off Value */
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#define GCLK_GENCTRL_OOV (0x1ul << GCLK_GENCTRL_OOV_Pos)
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#define GCLK_GENCTRL_OE_Pos 11 /**< \brief (GCLK_GENCTRL) Output Enable */
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#define GCLK_GENCTRL_OE (0x1ul << GCLK_GENCTRL_OE_Pos)
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#define GCLK_GENCTRL_DIVSEL_Pos 12 /**< \brief (GCLK_GENCTRL) Divide Selection */
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#define GCLK_GENCTRL_DIVSEL (0x1ul << GCLK_GENCTRL_DIVSEL_Pos)
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#define GCLK_GENCTRL_RUNSTDBY_Pos 13 /**< \brief (GCLK_GENCTRL) Run in Standby */
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#define GCLK_GENCTRL_RUNSTDBY (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos)
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#define GCLK_GENCTRL_DIV_Pos 16 /**< \brief (GCLK_GENCTRL) Division Factor */
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#define GCLK_GENCTRL_DIV_Msk (0xFFFFul << GCLK_GENCTRL_DIV_Pos)
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#define GCLK_GENCTRL_DIV(value) ((GCLK_GENCTRL_DIV_Msk & ((value) << GCLK_GENCTRL_DIV_Pos)))
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#define GCLK_GENCTRL_MASK 0xFFFF3F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */
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/* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef union {
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struct {
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uint32_t GEN:4; /*!< bit: 0.. 3 Generic Clock Generator */
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uint32_t :2; /*!< bit: 4.. 5 Reserved */
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uint32_t CHEN:1; /*!< bit: 6 Channel Enable */
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uint32_t WRTLOCK:1; /*!< bit: 7 Write Lock */
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uint32_t :24; /*!< bit: 8..31 Reserved */
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} bit; /*!< Structure used for bit access */
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uint32_t reg; /*!< Type used for register access */
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} GCLK_PCHCTRL_Type;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#define GCLK_PCHCTRL_OFFSET 0x80 /**< \brief (GCLK_PCHCTRL offset) Peripheral Clock Control */
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#define GCLK_PCHCTRL_RESETVALUE 0x00000000ul /**< \brief (GCLK_PCHCTRL reset_value) Peripheral Clock Control */
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#define GCLK_PCHCTRL_GEN_Pos 0 /**< \brief (GCLK_PCHCTRL) Generic Clock Generator */
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#define GCLK_PCHCTRL_GEN_Msk (0xFul << GCLK_PCHCTRL_GEN_Pos)
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#define GCLK_PCHCTRL_GEN(value) ((GCLK_PCHCTRL_GEN_Msk & ((value) << GCLK_PCHCTRL_GEN_Pos)))
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#define GCLK_PCHCTRL_GEN_GCLK0_Val 0x0ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 0 */
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#define GCLK_PCHCTRL_GEN_GCLK1_Val 0x1ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 1 */
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#define GCLK_PCHCTRL_GEN_GCLK2_Val 0x2ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 2 */
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#define GCLK_PCHCTRL_GEN_GCLK3_Val 0x3ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 3 */
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#define GCLK_PCHCTRL_GEN_GCLK4_Val 0x4ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 4 */
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#define GCLK_PCHCTRL_GEN_GCLK5_Val 0x5ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 5 */
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#define GCLK_PCHCTRL_GEN_GCLK6_Val 0x6ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 6 */
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#define GCLK_PCHCTRL_GEN_GCLK7_Val 0x7ul /**< \brief (GCLK_PCHCTRL) Generic clock generator 7 */
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#define GCLK_PCHCTRL_GEN_GCLK0 (GCLK_PCHCTRL_GEN_GCLK0_Val << GCLK_PCHCTRL_GEN_Pos)
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#define GCLK_PCHCTRL_GEN_GCLK1 (GCLK_PCHCTRL_GEN_GCLK1_Val << GCLK_PCHCTRL_GEN_Pos)
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#define GCLK_PCHCTRL_GEN_GCLK2 (GCLK_PCHCTRL_GEN_GCLK2_Val << GCLK_PCHCTRL_GEN_Pos)
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#define GCLK_PCHCTRL_GEN_GCLK3 (GCLK_PCHCTRL_GEN_GCLK3_Val << GCLK_PCHCTRL_GEN_Pos)
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#define GCLK_PCHCTRL_GEN_GCLK4 (GCLK_PCHCTRL_GEN_GCLK4_Val << GCLK_PCHCTRL_GEN_Pos)
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#define GCLK_PCHCTRL_GEN_GCLK5 (GCLK_PCHCTRL_GEN_GCLK5_Val << GCLK_PCHCTRL_GEN_Pos)
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#define GCLK_PCHCTRL_GEN_GCLK6 (GCLK_PCHCTRL_GEN_GCLK6_Val << GCLK_PCHCTRL_GEN_Pos)
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#define GCLK_PCHCTRL_GEN_GCLK7 (GCLK_PCHCTRL_GEN_GCLK7_Val << GCLK_PCHCTRL_GEN_Pos)
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#define GCLK_PCHCTRL_CHEN_Pos 6 /**< \brief (GCLK_PCHCTRL) Channel Enable */
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#define GCLK_PCHCTRL_CHEN (0x1ul << GCLK_PCHCTRL_CHEN_Pos)
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#define GCLK_PCHCTRL_WRTLOCK_Pos 7 /**< \brief (GCLK_PCHCTRL) Write Lock */
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#define GCLK_PCHCTRL_WRTLOCK (0x1ul << GCLK_PCHCTRL_WRTLOCK_Pos)
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#define GCLK_PCHCTRL_MASK 0x000000CFul /**< \brief (GCLK_PCHCTRL) MASK Register */
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/** \brief GCLK hardware registers */
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#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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typedef struct {
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__IO GCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */
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RoReg8 Reserved1[0x3];
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__I GCLK_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */
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RoReg8 Reserved2[0x18];
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__IO GCLK_GENCTRL_Type GENCTRL[9]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Generator Control */
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RoReg8 Reserved3[0x3C];
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__IO GCLK_PCHCTRL_Type PCHCTRL[36]; /**< \brief Offset: 0x80 (R/W 32) Peripheral Clock Control */
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} Gclk;
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#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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/*@}*/
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#endif /* _SAML21_GCLK_COMPONENT_ */
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